VirtualBox

Changeset 86014 in vbox for trunk/src


Ignore:
Timestamp:
Sep 3, 2020 7:31:53 AM (4 years ago)
Author:
vboxsync
Message:

AMD IOMMU: bugref:9654 STAM counters.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

    r85996 r86014  
    180180    /** @name PCI: Base capability block registers.
    181181     * @{ */
    182     IOMMU_BAR_T                 IommuBar;            /**< IOMMU base address register. */
     182    IOMMU_BAR_T                 IommuBar;               /**< IOMMU base address register. */
    183183    /** @} */
    184184
    185185    /** @name MMIO: Control and status registers.
    186186     * @{ */
    187     DEV_TAB_BAR_T               aDevTabBaseAddrs[8]; /**< Device table base address registers. */
    188     CMD_BUF_BAR_T               CmdBufBaseAddr;      /**< Command buffer base address register. */
    189     EVT_LOG_BAR_T               EvtLogBaseAddr;      /**< Event log base address register. */
    190     IOMMU_CTRL_T                Ctrl;                /**< IOMMU control register. */
    191     IOMMU_EXCL_RANGE_BAR_T      ExclRangeBaseAddr;   /**< IOMMU exclusion range base register. */
    192     IOMMU_EXCL_RANGE_LIMIT_T    ExclRangeLimit;      /**< IOMMU exclusion range limit. */
    193     IOMMU_EXT_FEAT_T            ExtFeat;             /**< IOMMU extended feature register. */
     187    DEV_TAB_BAR_T               aDevTabBaseAddrs[8];    /**< Device table base address registers. */
     188    CMD_BUF_BAR_T               CmdBufBaseAddr;         /**< Command buffer base address register. */
     189    EVT_LOG_BAR_T               EvtLogBaseAddr;         /**< Event log base address register. */
     190    IOMMU_CTRL_T                Ctrl;                   /**< IOMMU control register. */
     191    IOMMU_EXCL_RANGE_BAR_T      ExclRangeBaseAddr;      /**< IOMMU exclusion range base register. */
     192    IOMMU_EXCL_RANGE_LIMIT_T    ExclRangeLimit;         /**< IOMMU exclusion range limit. */
     193    IOMMU_EXT_FEAT_T            ExtFeat;                /**< IOMMU extended feature register. */
    194194    /** @} */
    195195
    196196    /** @name MMIO: PPR Log registers.
    197197     * @{ */
    198     PPR_LOG_BAR_T               PprLogBaseAddr;      /**< PPR Log base address register. */
    199     IOMMU_HW_EVT_HI_T           HwEvtHi;             /**< IOMMU hardware event register (Hi). */
    200     IOMMU_HW_EVT_LO_T           HwEvtLo;             /**< IOMMU hardware event register (Lo). */
    201     IOMMU_HW_EVT_STATUS_T       HwEvtStatus;         /**< IOMMU hardware event status. */
     198    PPR_LOG_BAR_T               PprLogBaseAddr;         /**< PPR Log base address register. */
     199    IOMMU_HW_EVT_HI_T           HwEvtHi;                /**< IOMMU hardware event register (Hi). */
     200    IOMMU_HW_EVT_LO_T           HwEvtLo;                /**< IOMMU hardware event register (Lo). */
     201    IOMMU_HW_EVT_STATUS_T       HwEvtStatus;            /**< IOMMU hardware event status. */
    202202    /** @} */
    203203
    … …  
    206206    /** @name MMIO: Guest Virtual-APIC Log registers.
    207207     * @{ */
    208     GALOG_BAR_T                 GALogBaseAddr;       /**< Guest Virtual-APIC Log base address register. */
    209     GALOG_TAIL_ADDR_T           GALogTailAddr;       /**< Guest Virtual-APIC Log Tail address register. */
     208    GALOG_BAR_T                 GALogBaseAddr;          /**< Guest Virtual-APIC Log base address register. */
     209    GALOG_TAIL_ADDR_T           GALogTailAddr;          /**< Guest Virtual-APIC Log Tail address register. */
    210210    /** @} */
    211211
    212212    /** @name MMIO: Alternate PPR and Event Log registers.
    213213     *  @{ */
    214     PPR_LOG_B_BAR_T             PprLogBBaseAddr;     /**< PPR Log B base address register. */
    215     EVT_LOG_B_BAR_T             EvtLogBBaseAddr;     /**< Event Log B base address register. */
     214    PPR_LOG_B_BAR_T             PprLogBBaseAddr;        /**< PPR Log B base address register. */
     215    EVT_LOG_B_BAR_T             EvtLogBBaseAddr;        /**< Event Log B base address register. */
    216216    /** @} */
    217217
    218218    /** @name MMIO: Device-specific feature registers.
    219219     * @{ */
    220     DEV_SPECIFIC_FEAT_T         DevSpecificFeat;     /**< Device-specific feature extension register (DSFX). */
    221     DEV_SPECIFIC_CTRL_T         DevSpecificCtrl;     /**< Device-specific control extension register (DSCX). */
    222     DEV_SPECIFIC_STATUS_T       DevSpecificStatus;   /**< Device-specific status extension register (DSSX). */
     220    DEV_SPECIFIC_FEAT_T         DevSpecificFeat;        /**< Device-specific feature extension register (DSFX). */
     221    DEV_SPECIFIC_CTRL_T         DevSpecificCtrl;        /**< Device-specific control extension register (DSCX). */
     222    DEV_SPECIFIC_STATUS_T       DevSpecificStatus;      /**< Device-specific status extension register (DSSX). */
    223223    /** @} */
    224224
    225225    /** @name MMIO: MSI Capability Block registers.
    226226     * @{ */
    227     MSI_MISC_INFO_T             MiscInfo;            /**< MSI Misc. info registers / MSI Vector registers. */
     227    MSI_MISC_INFO_T             MiscInfo;               /**< MSI Misc. info registers / MSI Vector registers. */
    228228    /** @} */
    229229
    230230    /** @name MMIO: Performance Optimization Control registers.
    231231     *  @{ */
    232     IOMMU_PERF_OPT_CTRL_T       PerfOptCtrl;         /**< IOMMU Performance optimization control register. */
     232    IOMMU_PERF_OPT_CTRL_T       PerfOptCtrl;            /**< IOMMU Performance optimization control register. */
    233233    /** @} */
    234234
    235235    /** @name MMIO: x2APIC Control registers.
    236236     * @{ */
    237     IOMMU_XT_GEN_INTR_CTRL_T    XtGenIntrCtrl;       /**< IOMMU X2APIC General interrupt control register. */
    238     IOMMU_XT_PPR_INTR_CTRL_T    XtPprIntrCtrl;       /**< IOMMU X2APIC PPR interrupt control register. */
    239     IOMMU_XT_GALOG_INTR_CTRL_T  XtGALogIntrCtrl;     /**< IOMMU X2APIC Guest Log interrupt control register. */
     237    IOMMU_XT_GEN_INTR_CTRL_T    XtGenIntrCtrl;          /**< IOMMU X2APIC General interrupt control register. */
     238    IOMMU_XT_PPR_INTR_CTRL_T    XtPprIntrCtrl;          /**< IOMMU X2APIC PPR interrupt control register. */
     239    IOMMU_XT_GALOG_INTR_CTRL_T  XtGALogIntrCtrl;        /**< IOMMU X2APIC Guest Log interrupt control register. */
    240240    /** @} */
    241241
    242242    /** @name MMIO: MARC registers.
    243243     * @{ */
    244     MARC_APER_T                 aMarcApers[4];       /**< MARC Aperture Registers. */
     244    MARC_APER_T                 aMarcApers[4];          /**< MARC Aperture Registers. */
    245245    /** @} */
    246246
    247247    /** @name MMIO: Reserved register.
    248248     *  @{ */
    249     IOMMU_RSVD_REG_T            RsvdReg;             /**< IOMMU Reserved Register. */
     249    IOMMU_RSVD_REG_T            RsvdReg;                /**< IOMMU Reserved Register. */
    250250    /** @} */
    251251
    252252    /** @name MMIO: Command and Event Log pointer registers.
    253253     * @{ */
    254     CMD_BUF_HEAD_PTR_T          CmdBufHeadPtr;       /**< Command buffer head pointer register. */
    255     CMD_BUF_TAIL_PTR_T          CmdBufTailPtr;       /**< Command buffer tail pointer register. */
    256     EVT_LOG_HEAD_PTR_T          EvtLogHeadPtr;       /**< Event log head pointer register. */
    257     EVT_LOG_TAIL_PTR_T          EvtLogTailPtr;       /**< Event log tail pointer register. */
     254    CMD_BUF_HEAD_PTR_T          CmdBufHeadPtr;          /**< Command buffer head pointer register. */
     255    CMD_BUF_TAIL_PTR_T          CmdBufTailPtr;          /**< Command buffer tail pointer register. */
     256    EVT_LOG_HEAD_PTR_T          EvtLogHeadPtr;          /**< Event log head pointer register. */
     257    EVT_LOG_TAIL_PTR_T          EvtLogTailPtr;          /**< Event log tail pointer register. */
    258258    /** @} */
    259259
    260260    /** @name MMIO: Command and Event Status register.
    261261     * @{ */
    262     IOMMU_STATUS_T              Status;              /**< IOMMU status register. */
     262    IOMMU_STATUS_T              Status;                 /**< IOMMU status register. */
    263263    /** @} */
    264264
    265265    /** @name MMIO: PPR Log Head and Tail pointer registers.
    266266     * @{ */
    267     PPR_LOG_HEAD_PTR_T          PprLogHeadPtr;       /**< IOMMU PPR log head pointer register. */
    268     PPR_LOG_TAIL_PTR_T          PprLogTailPtr;       /**< IOMMU PPR log tail pointer register. */
     267    PPR_LOG_HEAD_PTR_T          PprLogHeadPtr;          /**< IOMMU PPR log head pointer register. */
     268    PPR_LOG_TAIL_PTR_T          PprLogTailPtr;          /**< IOMMU PPR log tail pointer register. */
    269269    /** @} */
    270270
    271271    /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
    272272     * @{ */
    273     GALOG_HEAD_PTR_T            GALogHeadPtr;        /**< Guest Virtual-APIC log head pointer register. */
    274     GALOG_TAIL_PTR_T            GALogTailPtr;        /**< Guest Virtual-APIC log tail pointer register. */
     273    GALOG_HEAD_PTR_T            GALogHeadPtr;           /**< Guest Virtual-APIC log head pointer register. */
     274    GALOG_TAIL_PTR_T            GALogTailPtr;           /**< Guest Virtual-APIC log tail pointer register. */
    275275    /** @} */
    276276
    277277    /** @name MMIO: PPR Log B Head and Tail pointer registers.
    278278     *  @{ */
    279     PPR_LOG_B_HEAD_PTR_T        PprLogBHeadPtr;      /**< PPR log B head pointer register. */
    280     PPR_LOG_B_TAIL_PTR_T        PprLogBTailPtr;      /**< PPR log B tail pointer register. */
     279    PPR_LOG_B_HEAD_PTR_T        PprLogBHeadPtr;         /**< PPR log B head pointer register. */
     280    PPR_LOG_B_TAIL_PTR_T        PprLogBTailPtr;         /**< PPR log B tail pointer register. */
    281281    /** @} */
    282282
    283283    /** @name MMIO: Event Log B Head and Tail pointer registers.
    284284     * @{ */
    285     EVT_LOG_B_HEAD_PTR_T        EvtLogBHeadPtr;      /**< Event log B head pointer register. */
    286     EVT_LOG_B_TAIL_PTR_T        EvtLogBTailPtr;      /**< Event log B tail pointer register. */
     285    EVT_LOG_B_HEAD_PTR_T        EvtLogBHeadPtr;         /**< Event log B head pointer register. */
     286    EVT_LOG_B_TAIL_PTR_T        EvtLogBTailPtr;         /**< Event log B tail pointer register. */
    287287    /** @} */
    288288
    … …  
    296296    /** @todo IOMMU: IOMMU Event counter registers. */
    297297
    298     /** @todo IOMMU: Stat counters. */
     298#ifdef VBOX_WITH_STATISTICS
     299    /** @name IOMMU: Stat counters.
     300     * @{ */
     301    STAMCOUNTER             StatMmioReadR3;             /**< Number of MMIO reads in R3. */
     302    STAMCOUNTER             StatMmioReadRZ;             /**< Number of MMIO reads in RZ. */
     303
     304    STAMCOUNTER             StatMmioWriteR3;            /**< Number of MMIO writes in R3. */
     305    STAMCOUNTER             StatMmioWriteRZ;            /**< Number of MMIO writes in RZ. */
     306
     307    STAMCOUNTER             StatMsiRemapR3;             /**< Number of MSI remap requests in R3. */
     308    STAMCOUNTER             StatMsiRemapRZ;             /**< Number of MSI remap requests in RZ. */
     309
     310    STAMCOUNTER             StatCmd;                    /**< Number of commands processed. */
     311    STAMCOUNTER             StatCmdCompWait;            /**< Number of Completion Wait commands processed. */
     312    STAMCOUNTER             StatCmdInvDte;              /**< Number of Invalidate DTE commands processed. */
     313    STAMCOUNTER             StatCmdInvIommuPages;       /**< Number of Invalidate IOMMU pages commands processed. */
     314    STAMCOUNTER             StatCmdInvIotlbPages;       /**< Number of Invalidate IOTLB pages commands processed. */
     315    STAMCOUNTER             StatCmdInvIntrTable;        /**< Number of Invalidate Interrupt Table commands processed. */
     316    STAMCOUNTER             StatCmdPrefIommuPages;      /**< Number of Prefetch IOMMU Pages commands processed. */
     317    STAMCOUNTER             StatCmdCompletePprReq;      /**< Number of Complete PPR Requests commands processed. */
     318    STAMCOUNTER             StatCmdInvIommuAll;         /**< Number of Invalidate IOMMU All commands processed. */
     319    /** @} */
     320#endif
    299321} IOMMU;
    300322/** Pointer to the IOMMU device state. */
    … …  
    504526{
    505527    IOMMU_ASSERT_LOCKED(pDevIns);
    506     LogFlowFunc(("\n"));
     528    Log5Func(("\n"));
    507529
    508530    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
    … …  
    510532    if (Status.n.u1CmdBufRunning)
    511533    {
    512         LogFlowFunc(("Signaling command thread\n"));
     534        Log5Func(("Signaling command thread\n"));
    513535        PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
    514536    }
    … …  
    27172739
    27182740    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
     2741    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
     2742
    27192743    LogFlowFunc(("uDevId=%#x\n", uDevId));
    27202744
    … …  
    27422766    Assert(!(off & (cb - 1)));
    27432767
     2768    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
     2769    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
     2770
    27442771    uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
    27452772    return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
    … …  
    27552782    Assert(cb == 4 || cb == 8);
    27562783    Assert(!(off & (cb - 1)));
     2784
     2785    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
     2786    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
    27572787
    27582788    uint64_t uResult;
    … …  
    27862816
    27872817    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
     2818    STAM_COUNTER_INC(&pThis->StatCmd);
     2819
    27882820    uint8_t const bCmd = pCmd->n.u4Opcode;
    27892821    switch (bCmd)
    … …  
    27912823        case IOMMU_CMD_COMPLETION_WAIT:
    27922824        {
     2825            STAM_COUNTER_INC(&pThis->StatCmdCompWait);
     2826
    27932827            PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
    27942828            AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
    … …  
    28362870            /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
    28372871             *        then. */
     2872            STAM_COUNTER_INC(&pThis->StatCmdInvDte);
    28382873            return VINF_SUCCESS;
    28392874        }
    … …  
    28432878            /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
    28442879             *        then. */
     2880            STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
    28452881            return VINF_SUCCESS;
    28462882        }
    … …  
    28482884        case IOMMU_CMD_INV_IOTLB_PAGES:
    28492885        {
     2886            STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
     2887
    28502888            uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
    28512889            if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
    … …  
    28622900            /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
    28632901             *        then. */
     2902            STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
    28642903            return VINF_SUCCESS;
    28652904        }
    … …  
    28672906        case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
    28682907        {
     2908            STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
    28692909            if (pThis->ExtFeat.n.u1PrefetchSup)
    28702910            {
    … …  
    28782918        case IOMMU_CMD_COMPLETE_PPR_REQ:
    28792919        {
     2920            STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
     2921
    28802922            /* We don't support PPR requests yet. */
    28812923            Assert(!pThis->ExtFeat.n.u1PprSup);
    … …  
    28862928        case IOMMU_CMD_INV_IOMMU_ALL:
    28872929        {
     2930            STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
     2931
    28882932            if (pThis->ExtFeat.n.u1InvAllSup)
    28892933            {
    … …  
    28962940    }
    28972941
     2942    STAM_COUNTER_DEC(&pThis->StatCmd);
    28982943    LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
    28992944    iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
    … …  
    29312976                if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
    29322977                    break;
    2933                 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
     2978                Log5Func(("Woken up with rc=%Rrc\n", rc));
    29342979                ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
    29352980            }
    … …  
    29502995        if (Status.n.u1CmdBufRunning)
    29512996        {
    2952             LogFlowFunc(("Command buffer running\n"));
    2953 
    29542997            /* Get the offset we need to read the command from memory (circular buffer offset). */
    29552998            uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
    … …  
    39834026    rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
    39844027    AssertLogRelRCReturn(rc, rc);
     4028
     4029# ifdef VBOX_WITH_STATISTICS
     4030    /*
     4031     * Statistics.
     4032     */
     4033    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3,  STAMTYPE_COUNTER, "R3/MmioReadR3",  STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
     4034    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ,  STAMTYPE_COUNTER, "RZ/MmioReadRZ",  STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
     4035
     4036    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
     4037    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
     4038
     4039    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemapR3", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
     4040    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRZ", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
     4041
     4042    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
     4043    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
     4044    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
     4045    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
     4046    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
     4047    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
     4048    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
     4049    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
     4050    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
     4051# endif
    39854052
    39864053    /*
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