Changeset 86248 in vbox
- Timestamp:
- Sep 23, 2020 5:01:08 PM (4 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r86237 r86248 169 169 # ifdef RT_OS_LINUX 170 170 # ifdef IN_RING3 171 # include "DevVGA-SVGA3d-glLdr.h"171 # include "DevVGA-SVGA3d-glLdr.h" 172 172 # endif 173 173 # endif … … 642 642 #define SVGA_CASE_ID2STR(idx) case idx: return #idx 643 643 644 #if def LOG_ENABLED644 #if defined(LOG_ENABLED) || defined(VBOX_STRICT) 645 645 646 646 /** … … 730 730 } 731 731 732 # ifdef IN_RING3732 # ifdef IN_RING3 733 733 /** 734 734 * FIFO command name lookup … … 961 961 # endif /* IN_RING3 */ 962 962 963 #endif /* LOG_ENABLED */963 #endif /* LOG_ENABLED || VBOX_STRICT*/ 964 964 #ifdef IN_RING3 965 965 … … 3183 3183 # define VMSVGA_3D_CMD_NOTIMPL() \ 3184 3184 if (1) { \ 3185 AssertMsgFailed(("Not implemented %d %s\n", cmdId, vmsvgaR3FifoCmdToString(cmdId))); \3185 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \ 3186 3186 } else do {} while (0) 3187 3187 … … 3191 3191 * @param pThis The shared VGA/VMSVGA state. 3192 3192 * @param pThisCC The VGA/VMSVGA state for the current context. 3193 * @param cmdIdSVGA_3D_CMD_* command identifier.3193 * @param enmCmdId SVGA_3D_CMD_* command identifier. 3194 3194 * @param cbCmd Size of the command in bytes. 3195 3195 * @param pvCmd Pointer to the command. 3196 3196 * @returns VBox status code if an error was detected parsing a command. 3197 3197 */ 3198 static int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t cmdId, uint32_t cbCmd, void const *pvCmd)3198 static int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd) 3199 3199 { 3200 3200 int rcParse = VINF_SUCCESS; 3201 3201 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State; 3202 3202 3203 switch ( cmdId)3203 switch (enmCmdId) 3204 3204 { 3205 3205 case SVGA_3D_CMD_SURFACE_DEFINE: … … 3470 3470 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd; 3471 3471 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3472 if ( cmdId == SVGA_3D_CMD_PRESENT)3472 if (enmCmdId == SVGA_3D_CMD_PRESENT) 3473 3473 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent); 3474 3474 else … … 3620 3620 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd; 3621 3621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3622 VMSVGA_3D_CMD_NOTIMPL(); 3622 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3623 3623 break; 3624 3624 } … … 3635 3635 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd; 3636 3636 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3637 VMSVGA_3D_CMD_NOTIMPL(); 3637 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3638 3638 break; 3639 3639 } … … 3643 3643 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd; 3644 3644 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3645 VMSVGA_3D_CMD_NOTIMPL(); 3645 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3646 3646 break; 3647 3647 } … … 3651 3651 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd; 3652 3652 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3653 VMSVGA_3D_CMD_NOTIMPL(); 3653 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3654 3654 break; 3655 3655 } … … 3659 3659 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd; 3660 3660 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3661 VMSVGA_3D_CMD_NOTIMPL(); 3661 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3662 3662 break; 3663 3663 } … … 3667 3667 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd; 3668 3668 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3669 VMSVGA_3D_CMD_NOTIMPL(); 3669 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3670 3670 break; 3671 3671 } … … 3675 3675 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd; 3676 3676 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3677 VMSVGA_3D_CMD_NOTIMPL(); 3677 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3678 3678 break; 3679 3679 } … … 3683 3683 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd; 3684 3684 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3685 VMSVGA_3D_CMD_NOTIMPL(); 3685 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3686 3686 break; 3687 3687 } … … 3691 3691 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd; 3692 3692 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3693 VMSVGA_3D_CMD_NOTIMPL(); 3693 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3694 3694 break; 3695 3695 } … … 3699 3699 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd; 3700 3700 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3701 VMSVGA_3D_CMD_NOTIMPL(); 3701 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3702 3702 break; 3703 3703 } … … 3707 3707 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd; 3708 3708 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3709 VMSVGA_3D_CMD_NOTIMPL(); 3709 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3710 3710 break; 3711 3711 } … … 3721 3721 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd; 3722 3722 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3723 VMSVGA_3D_CMD_NOTIMPL(); 3723 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3724 3724 break; 3725 3725 } … … 3729 3729 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd; 3730 3730 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3731 VMSVGA_3D_CMD_NOTIMPL(); 3731 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3732 3732 break; 3733 3733 } … … 3737 3737 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd; 3738 3738 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3739 VMSVGA_3D_CMD_NOTIMPL(); 3739 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3740 3740 break; 3741 3741 } … … 3745 3745 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd; 3746 3746 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3747 VMSVGA_3D_CMD_NOTIMPL(); 3747 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3748 3748 break; 3749 3749 } … … 3753 3753 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd; 3754 3754 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3755 VMSVGA_3D_CMD_NOTIMPL(); 3755 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3756 3756 break; 3757 3757 } … … 3761 3761 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd; 3762 3762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3763 VMSVGA_3D_CMD_NOTIMPL(); 3763 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3764 3764 break; 3765 3765 } … … 3769 3769 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd; 3770 3770 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3771 VMSVGA_3D_CMD_NOTIMPL(); 3771 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3772 3772 break; 3773 3773 } … … 3777 3777 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd; 3778 3778 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3779 VMSVGA_3D_CMD_NOTIMPL(); 3779 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3780 3780 break; 3781 3781 } … … 3785 3785 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd; 3786 3786 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3787 VMSVGA_3D_CMD_NOTIMPL(); 3787 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3788 3788 break; 3789 3789 } … … 3793 3793 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd; 3794 3794 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3795 VMSVGA_3D_CMD_NOTIMPL(); 3795 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3796 3796 break; 3797 3797 } … … 3801 3801 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd; 3802 3802 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3803 VMSVGA_3D_CMD_NOTIMPL(); 3803 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3804 3804 break; 3805 3805 } … … 3809 3809 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd; 3810 3810 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3811 VMSVGA_3D_CMD_NOTIMPL(); 3811 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3812 3812 break; 3813 3813 } … … 3817 3817 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd; 3818 3818 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3819 VMSVGA_3D_CMD_NOTIMPL(); 3819 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3820 3820 break; 3821 3821 } … … 3825 3825 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd; 3826 3826 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3827 VMSVGA_3D_CMD_NOTIMPL(); 3827 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3828 3828 break; 3829 3829 } … … 3833 3833 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd; 3834 3834 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3835 VMSVGA_3D_CMD_NOTIMPL(); 3835 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3836 3836 break; 3837 3837 } … … 3841 3841 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd; 3842 3842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3843 VMSVGA_3D_CMD_NOTIMPL(); 3843 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3844 3844 break; 3845 3845 } … … 3849 3849 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd; 3850 3850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3851 VMSVGA_3D_CMD_NOTIMPL(); 3851 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3852 3852 break; 3853 3853 } … … 3857 3857 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd; 3858 3858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3859 VMSVGA_3D_CMD_NOTIMPL(); 3859 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3860 3860 break; 3861 3861 } … … 3865 3865 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd; 3866 3866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3867 VMSVGA_3D_CMD_NOTIMPL(); 3867 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3868 3868 break; 3869 3869 } … … 3873 3873 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd; 3874 3874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3875 VMSVGA_3D_CMD_NOTIMPL(); 3875 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3876 3876 break; 3877 3877 } … … 3881 3881 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd; 3882 3882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3883 VMSVGA_3D_CMD_NOTIMPL(); 3883 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3884 3884 break; 3885 3885 } … … 3889 3889 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd; 3890 3890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3891 VMSVGA_3D_CMD_NOTIMPL(); 3891 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3892 3892 break; 3893 3893 } … … 3897 3897 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd; 3898 3898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3899 VMSVGA_3D_CMD_NOTIMPL(); 3899 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3900 3900 break; 3901 3901 } … … 3911 3911 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd; 3912 3912 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3913 VMSVGA_3D_CMD_NOTIMPL(); 3913 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3914 3914 break; 3915 3915 } … … 3926 3926 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd; 3927 3927 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3928 VMSVGA_3D_CMD_NOTIMPL(); 3928 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3929 3929 break; 3930 3930 } … … 3934 3934 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd; 3935 3935 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3936 VMSVGA_3D_CMD_NOTIMPL(); 3936 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3937 3937 break; 3938 3938 } … … 3942 3942 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd; 3943 3943 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3944 VMSVGA_3D_CMD_NOTIMPL(); 3944 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3945 3945 break; 3946 3946 } … … 3950 3950 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd; 3951 3951 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3952 VMSVGA_3D_CMD_NOTIMPL(); 3952 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3953 3953 break; 3954 3954 } … … 3958 3958 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd; 3959 3959 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3960 VMSVGA_3D_CMD_NOTIMPL(); 3960 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3961 3961 break; 3962 3962 } … … 3966 3966 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd; 3967 3967 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3968 VMSVGA_3D_CMD_NOTIMPL(); 3968 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3969 3969 break; 3970 3970 } … … 3974 3974 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd; 3975 3975 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3976 VMSVGA_3D_CMD_NOTIMPL(); 3976 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3977 3977 break; 3978 3978 } … … 3982 3982 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd; 3983 3983 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3984 VMSVGA_3D_CMD_NOTIMPL(); 3984 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3985 3985 break; 3986 3986 } … … 3990 3990 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd; 3991 3991 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 3992 VMSVGA_3D_CMD_NOTIMPL(); 3992 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 3993 3993 break; 3994 3994 } … … 3998 3998 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd; 3999 3999 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4000 VMSVGA_3D_CMD_NOTIMPL(); 4000 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4001 4001 break; 4002 4002 } … … 4006 4006 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd; 4007 4007 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4008 VMSVGA_3D_CMD_NOTIMPL(); 4008 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4009 4009 break; 4010 4010 } … … 4014 4014 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd; 4015 4015 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4016 VMSVGA_3D_CMD_NOTIMPL(); 4016 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4017 4017 break; 4018 4018 } … … 4031 4031 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd; 4032 4032 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4033 VMSVGA_3D_CMD_NOTIMPL(); 4033 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4034 4034 break; 4035 4035 } … … 4039 4039 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd; 4040 4040 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4041 VMSVGA_3D_CMD_NOTIMPL(); 4041 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4042 4042 break; 4043 4043 } … … 4053 4053 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd; 4054 4054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4055 VMSVGA_3D_CMD_NOTIMPL(); 4055 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4056 4056 break; 4057 4057 } … … 4061 4061 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd; 4062 4062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4063 VMSVGA_3D_CMD_NOTIMPL(); 4063 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4064 4064 break; 4065 4065 } … … 4069 4069 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd; 4070 4070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4071 VMSVGA_3D_CMD_NOTIMPL(); 4071 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); 4072 4072 break; 4073 4073 } … … 4089 4089 default: 4090 4090 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds); 4091 ASSERT_GUEST_MSG_FAILED((" cmdId=%d\n", cmdId));4091 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId)); 4092 4092 rcParse = VERR_NOT_IMPLEMENTED; 4093 4093 break; … … 5848 5848 5849 5849 /* Command data begins after the 32 bit command length. */ 5850 int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, cmdId, *pcbMore, pcbMore + 1);5850 int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1); 5851 5851 if (RT_SUCCESS(rc)) 5852 5852 { /* likely */ } … … 7079 7079 } 7080 7080 7081 vmsvgaR3Process3dCmd(pThis, pThisCC, enmCmdId, cbCmd, pu32Cmd);7081 vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd); 7082 7082 } 7083 7083 else
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