Changeset 86254 in vbox

Timestamp:

Sep 24, 2020 5:56:29 AM (4 years ago)

Author:

vboxsync

Message:

AMD IOMMU: bugref:9654 Add some more stat counters.

File:

• trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (9 diffs)

trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

@@ -316 +316 @@
     STAMCOUNTER             StatMsiRemapR3;             /**< Number of MSI remap requests in R3. */
     STAMCOUNTER             StatMsiRemapRZ;             /**< Number of MSI remap requests in RZ. */
+
+    STAMCOUNTER             StatMemReadR3;              /**< Number of memory read translation requests in R3. */
+    STAMCOUNTER             StatMemReadRZ;              /**< Number of memory read translation requests in RZ. */
+    STAMCOUNTER             StatMemWriteR3;             /**< Number of memory write translation requests in R3. */
+    STAMCOUNTER             StatMemWriteRZ;             /**< Number of memory write translation requests in RZ. */
 
     STAMCOUNTER             StatCmd;                    /**< Number of commands processed. */
@@ -2032 +2037 @@
     }
 
-    /* If a read handler doesn't exist, it's reserved or unknown register. */
+    /* If a read handler doesn't exist, it's a reserved or unknown register. */
     if (pReg->pfnRead)
     { /* likely */ }
@@ -2989 +2994 @@
 
         /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
-        if (   !pThis->ExclRangeBaseAddr.n.u1ExclEnable
+        if (   !pThis->ExclRangeBaseAddr.n.u1ExclEnable         /** @todo lock or make atomic read? */
             || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
         { /* likely */ }
@@ -3069 +3074 @@
 
     PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
-    LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
 
     /* Addresses are forwarded without translation when the IOMMU is disabled. */
@@ -3075 +3079 @@
     if (Ctrl.n.u1IommuEn)
     {
+        STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
+        LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
+
         /** @todo IOMMU: IOTLB cache lookup. */
 
@@ -3107 +3114 @@
 
     PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
-    LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
 
     /* Addresses are forwarded without translation when the IOMMU is disabled. */
@@ -3113 +3119 @@
     if (Ctrl.n.u1IommuEn)
     {
+        STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
+        LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
+
         /** @todo IOMMU: IOTLB cache lookup. */
 
@@ -4893 +4902 @@
      */
     rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
-                             NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING,
+                             NULL /* pvUser */,
+                               IOMMMIO_FLAGS_READ_DWORD_QWORD
+                             | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
+                             | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
+                             | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
                              "AMD-IOMMU", &pThis->hMmio);
     AssertLogRelRCReturn(rc, rc);
@@ -4919 +4932 @@
      * Statistics.
      */
-    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3,  STAMTYPE_COUNTER, "R3/MmioReadR3",  STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
-    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ,  STAMTYPE_COUNTER, "RZ/MmioReadRZ",  STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
-
-    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
-    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
-
-    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemapR3", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
-    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRZ", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3,  STAMTYPE_COUNTER, "R3/MmioRead",  STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ,  STAMTYPE_COUNTER, "RZ/MmioRead",  STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
+
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
+
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
+
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3,  STAMTYPE_COUNTER, "R3/MemRead",  STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ,  STAMTYPE_COUNTER, "RZ/MemRead",  STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
+
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3,  STAMTYPE_COUNTER, "R3/MemWrite",  STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ,  STAMTYPE_COUNTER, "RZ/MemWrite",  STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
 
     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");