VirtualBox

Changeset 86339 in vbox


Ignore:
Timestamp:
Sep 30, 2020 7:22:13 AM (4 years ago)
Author:
vboxsync
Message:

AMD IOMMU: bugref:9654 Logging.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

    r86319 r86339  
    3838*********************************************************************************************************************************/
    3939/** Release log prefix string. */
    40 #define IOMMU_LOG_PFX                               "IOMMU-AMD"
     40#define IOMMU_LOG_PFX                               "AMD-IOMMU"
    4141/** The current saved state version. */
    4242#define IOMMU_SAVED_STATE_VERSION                   1
    … …  
    27412741        if ((fAccess & fDtePerm) != fAccess)
    27422742        {
    2743             LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
     2743            LogFunc(("Access denied for IOVA %#RX64. uDevId=%#x fAccess=%#x fDtePerm=%#x\n", uIova, uDevId, fAccess, fDtePerm));
    27442744            return VERR_IOMMU_ADDR_ACCESS_DENIED;
    27452745        }
    … …  
    27582758         *        raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
    27592759         *        I'm just going with I/O page fault. */
    2760         LogFunc(("Invalid root page table level %#x -> IOPF\n", uMaxLevel));
     2760        LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
    27612761        EVT_IO_PAGE_FAULT_T EvtIoPageFault;
    27622762        iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
    … …  
    28312831        else
    28322832        {
    2833             LogFunc(("Page table entry not present -> IOPF\n"));
     2833            LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
    28342834            EVT_IO_PAGE_FAULT_T EvtIoPageFault;
    28352835            iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
    … …  
    28452845        else
    28462846        {
    2847             LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF\n", fAccess, fPtePerm));
     2847            LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
    28482848            EVT_IO_PAGE_FAULT_T EvtIoPageFault;
    28492849            iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
    … …  
    46694669     * Resets read-write portion of the IOMMU state.
    46704670     *
    4671      * State data not initialized here is expected to be initialized during
     4671     * NOTE! State not initialized here is expected to be initialized during
    46724672     * device construction and remain read-only through the lifetime of the VM.
    46734673     */
    … …  
    48334833    /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
    48344834    PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
    4835                         RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID,    0xf)     /* RO - Secure Device capability block */
    4836                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR,   IOMMU_PCI_OFF_MSI_CAP_HDR)  /* RO - Offset to next capability */
    4837                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE,  0x3)     /* RO - IOMMU capability block */
    4838                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV,   0x1)     /* RO - IOMMU interface revision */
    4839                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0)     /* RO - Remote IOTLB support */
    4840                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0)     /* RO - HyperTransport Tunnel support */
    4841                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE,  0x0)     /* RO - Cache NP page table entries */
    4842                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP,   0x1)     /* RO - Extended Feature Register support */
    4843                       | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT,   0x1));   /* RO - Misc. Information Register support */
     4835                               RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID,    0xf)     /* RO - Secure Device capability block */
     4836                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR,   IOMMU_PCI_OFF_MSI_CAP_HDR)  /* RO - Next capability offset */
     4837                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE,  0x3)     /* RO - IOMMU capability block */
     4838                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV,   0x1)     /* RO - IOMMU interface revision */
     4839                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0)     /* RO - Remote IOTLB support */
     4840                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0)     /* RO - HyperTransport Tunnel support */
     4841                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE,  0x0)     /* RO - Cache NP page table entries */
     4842                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP,   0x1)     /* RO - Extended Feature Register support */
     4843                             | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT,   0x1));   /* RO - Misc. Information Register support */
    48444844
    48454845    /* Base Address Register. */
    … …  
    49904990     * NOTE! Fields here must match their corresponding field in the ACPI tables.
    49914991     */
    4992     /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
    4993      *        for me to see existing features that we might want to implement. Do it
    4994      *        later. */
     4992    /* Don't remove the commented lines below as it lets us see all features at a glance. */
    49954993    pThis->ExtFeat.u64 = 0;
    4996     pThis->ExtFeat.n.u1PrefetchSup           = 0;
    4997     pThis->ExtFeat.n.u1PprSup                = 0;
    4998     pThis->ExtFeat.n.u1X2ApicSup             = 0;
    4999     pThis->ExtFeat.n.u1NoExecuteSup          = 0;
    5000     pThis->ExtFeat.n.u1GstTranslateSup       = 0;
    5001     pThis->ExtFeat.n.u1InvAllSup             = 1;
    5002     pThis->ExtFeat.n.u1GstVirtApicSup        = 0;
    5003     pThis->ExtFeat.n.u1HwErrorSup            = 1;
    5004     pThis->ExtFeat.n.u1PerfCounterSup        = 0;
     4994    //pThis->ExtFeat.n.u1PrefetchSup           = 0;
     4995    //pThis->ExtFeat.n.u1PprSup                = 0;
     4996    //pThis->ExtFeat.n.u1X2ApicSup             = 0;
     4997    //pThis->ExtFeat.n.u1NoExecuteSup          = 0;
     4998    //pThis->ExtFeat.n.u1GstTranslateSup       = 0;
     4999    pThis->ExtFeat.n.u1InvAllSup               = 1;
     5000    //pThis->ExtFeat.n.u1GstVirtApicSup        = 0;
     5001    pThis->ExtFeat.n.u1HwErrorSup              = 1;
     5002    //pThis->ExtFeat.n.u1PerfCounterSup        = 0;
    50055003    AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
    50065004    pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
    5007     pThis->ExtFeat.n.u2GstAddrTranslateSize  = 0;   /* Requires GstTranslateSup */
    5008     pThis->ExtFeat.n.u2GstCr3RootTblLevel    = 0;   /* Requires GstTranslateSup */
    5009     pThis->ExtFeat.n.u2SmiFilterSup          = 0;
    5010     pThis->ExtFeat.n.u3SmiFilterCount        = 0;
    5011     pThis->ExtFeat.n.u3GstVirtApicModeSup    = 0;   /* Requires GstVirtApicSup */
    5012     pThis->ExtFeat.n.u2DualPprLogSup         = 0;
    5013     pThis->ExtFeat.n.u2DualEvtLogSup         = 0;
    5014     pThis->ExtFeat.n.u5MaxPasidSup           = 0;   /* Requires GstTranslateSup */
    5015     pThis->ExtFeat.n.u1UserSupervisorSup     = 0;
     5005    //pThis->ExtFeat.n.u2GstAddrTranslateSize  = 0;   /* Requires GstTranslateSup */
     5006    //pThis->ExtFeat.n.u2GstCr3RootTblLevel    = 0;   /* Requires GstTranslateSup */
     5007    //pThis->ExtFeat.n.u2SmiFilterSup          = 0;
     5008    //pThis->ExtFeat.n.u3SmiFilterCount        = 0;
     5009    //pThis->ExtFeat.n.u3GstVirtApicModeSup    = 0;   /* Requires GstVirtApicSup */
     5010    //pThis->ExtFeat.n.u2DualPprLogSup         = 0;
     5011    //pThis->ExtFeat.n.u2DualEvtLogSup         = 0;
     5012    //pThis->ExtFeat.n.u5MaxPasidSup           = 0;   /* Requires GstTranslateSup */
     5013    //pThis->ExtFeat.n.u1UserSupervisorSup     = 0;
    50165014    AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
    5017     pThis->ExtFeat.n.u2DevTabSegSup          = IOMMU_MAX_DEV_TAB_SEGMENTS;
    5018     pThis->ExtFeat.n.u1PprLogOverflowWarn    = 0;
    5019     pThis->ExtFeat.n.u1PprAutoRespSup        = 0;
    5020     pThis->ExtFeat.n.u2MarcSup               = 0;
    5021     pThis->ExtFeat.n.u1BlockStopMarkSup      = 0;
    5022     pThis->ExtFeat.n.u1PerfOptSup            = 0;
    5023     pThis->ExtFeat.n.u1MsiCapMmioSup         = 1;
    5024     pThis->ExtFeat.n.u1GstIoSup              = 0;
    5025     pThis->ExtFeat.n.u1HostAccessSup         = 0;
    5026     pThis->ExtFeat.n.u1EnhancedPprSup        = 0;
    5027     pThis->ExtFeat.n.u1AttrForwardSup        = 0;
    5028     pThis->ExtFeat.n.u1HostDirtySup          = 0;
    5029     pThis->ExtFeat.n.u1InvIoTlbTypeSup       = 0;
    5030     pThis->ExtFeat.n.u1GstUpdateDisSup       = 0;
    5031     pThis->ExtFeat.n.u1ForcePhysDstSup       = 0;
     5015    pThis->ExtFeat.n.u2DevTabSegSup            = IOMMU_MAX_DEV_TAB_SEGMENTS;
     5016    //pThis->ExtFeat.n.u1PprLogOverflowWarn    = 0;
     5017    //pThis->ExtFeat.n.u1PprAutoRespSup        = 0;
     5018    //pThis->ExtFeat.n.u2MarcSup               = 0;
     5019    //pThis->ExtFeat.n.u1BlockStopMarkSup      = 0;
     5020    //pThis->ExtFeat.n.u1PerfOptSup            = 0;
     5021    pThis->ExtFeat.n.u1MsiCapMmioSup           = 1;
     5022    //pThis->ExtFeat.n.u1GstIoSup              = 0;
     5023    //pThis->ExtFeat.n.u1HostAccessSup         = 0;
     5024    //pThis->ExtFeat.n.u1EnhancedPprSup        = 0;
     5025    //pThis->ExtFeat.n.u1AttrForwardSup        = 0;
     5026    //pThis->ExtFeat.n.u1HostDirtySup          = 0;
     5027    //pThis->ExtFeat.n.u1InvIoTlbTypeSup       = 0;
     5028    //pThis->ExtFeat.n.u1GstUpdateDisSup       = 0;
     5029    //pThis->ExtFeat.n.u1ForcePhysDstSup       = 0;
    50325030
    50335031    pThis->RsvdReg = 0;
    … …  
    50535051    iommuAmdR3Reset(pDevIns);
    50545052
     5053    LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
     5054            pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
     5055            pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
     5056            pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
     5057            pThis->ExtFeat.u64));
    50555058    return VINF_SUCCESS;
    50565059}
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