Changeset 86453 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Oct 5, 2020 5:42:00 PM (4 years ago)

Author:

vboxsync

Message:

VMM/PGM: Workaround for buggy gcc (10.2.1) clearing high dword of PDE. bugref:9841

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• PGMAll.cpp (modified) (1 diff)
• PGMAllBth.h (modified) (14 diffs)
• PGMAllShw.h (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -1756 +1756 @@
         pgmPoolCacheUsed(pPool, pShwPage);
     }
+
     /* The PDPT was cached or created; hook it up now and fill with the default value. */
+/** @todo r=bird: This is sub-optimal, gcc 10 generates a qword move of the address followed by
+ *        a byte write of the 0x7 flag value.  These two writes should be combined, but for that
+ *        we need to add/find the EPT flag defines. */
+/** @todo r=bird: use atomic writes here and maybe only update if really needed? */
     pPml4e->u           = pShwPage->Core.Key;
     pPml4e->n.u1Present = 1;

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -1249 +1249 @@
                          GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
                 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-                ASMAtomicWriteSize(pPdeDst, 0);
+                SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
                 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
                 PGM_INVL_VCPU_TLBS(pVCpu);
@@ -1292 +1292 @@
                      GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
             pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-            ASMAtomicWriteSize(pPdeDst, 0);
+            SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
             STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
             PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
@@ -1305 +1305 @@
         {
             pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
-            ASMAtomicWriteSize(pPdeDst, 0);
+            SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
             STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
             PGM_INVL_PG(pVCpu, GCPtrPage);
@@ -2038 +2038 @@
                         PdeDst.n.u1Write = PdeSrc.n.u1Write;
                     }
-                    ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+                    SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
                     Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
                           GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
@@ -2074 +2074 @@
      */
     pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
-    ASMAtomicWriteSize(pPdeDst, 0);
+    SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
 
     PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
@@ -2316 +2316 @@
             PdeDst.n.u1Accessed   = 1;
             PdeDst.au32[0]       &= ~PGM_PDFLAGS_TRACK_DIRTY;
-            ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+            SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
             PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
             return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;    /* restarts the instruction. */
@@ -2648 +2648 @@
                 }
             }
-            ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+            SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
             PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
             return VINF_SUCCESS;
@@ -2690 +2690 @@
                 PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | X86_PDE_AVL_MASK))
                          | GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
-                ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+                SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
                 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
 
@@ -2786 +2786 @@
                 PdeDst.b.u1Write = 0;
             }
-            ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+            SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
             PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
 
@@ -2978 +2978 @@
 
     /* Fetch the pgm pool shadow descriptor. */
+    /** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
     PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
     Assert(pShwPde);
@@ -3039 +3040 @@
             {
                 PdeDst.u &= X86_PDE_AVL_MASK;
-                PdeDst.u |= HCPhys;
                 PdeDst.n.u1Present   = 1;
                 PdeDst.n.u1Write     = 1;
@@ -3050 +3050 @@
                 PdeDst.n.u1User      = 1;
 #  endif
-                ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+                PdeDst.u |= HCPhys; /* Note! Must be done last of gcc v10.2.1 20200723 (Red Hat 10.2.1-1) may drop the top 32 bits. */
+                SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
 
                 Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
@@ -3112 +3113 @@
     /* Save the new PDE. */
     PdeDst.u &= X86_PDE_AVL_MASK;
-    PdeDst.u |= pShwPage->Core.Key;
     PdeDst.n.u1Present  = 1;
     PdeDst.n.u1Write    = 1;
@@ -3121 +3121 @@
     PdeDst.n.u1Accessed = 1;
 # endif
-    ASMAtomicWriteSize(pPdeDst, PdeDst.u);
+    PdeDst.u |= pShwPage->Core.Key; /* Note! Must be done last of gcc v10.2.1 20200723 (Red Hat 10.2.1-1) drops the top 32 bits. */
+    /** @todo r=bird: Stop using bitfields.  But we need to defined/find the EPT flags then. */
+    SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
 
     STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -31 +31 @@
 #undef SHW_PD_SHIFT
 #undef SHW_PD_MASK
+#undef SHW_PDE_ATOMIC_SET
+#undef SHW_PDE_ATOMIC_SET2
 #undef SHW_PTE_PG_MASK
 #undef SHW_PTE_IS_P
@@ -67 +69 @@
 # define SHW_PD_MASK                    X86_PD_MASK
 # define SHW_TOTAL_PD_ENTRIES           X86_PG_ENTRIES
+# define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU32(&(Pde).u, (uNew)); } while (0)
+# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU32(&(Pde).u, (Pde2).u); } while (0)
 # define SHW_PTE_PG_MASK                X86_PTE_PG_MASK
 # define SHW_PTE_IS_P(Pte)              ( (Pte).n.u1Present )
@@ -98 +102 @@
 # define SHW_PD_SHIFT                   EPT_PD_SHIFT
 # define SHW_PD_MASK                    EPT_PD_MASK
+# define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
+# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
 # define SHW_PTE_PG_MASK                EPT_PTE_PG_MASK
 # define SHW_PTE_IS_P(Pte)              ( (Pte).n.u1Present )  /* Approximation, works for us. */
@@ -133 +139 @@
 # define SHW_PD_SHIFT                   X86_PD_PAE_SHIFT
 # define SHW_PD_MASK                    X86_PD_PAE_MASK
+# define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
+# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
 # define SHW_PTE_PG_MASK                X86_PTE_PAE_PG_MASK
 # define SHW_PTE_IS_P(Pte)              PGMSHWPTEPAE_IS_P(Pte)