Changeset 86463 in vbox

Timestamp:

Oct 6, 2020 10:23:59 PM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

140768

Message:

VMM/PGMAllShw.h: More bitfield avoidance. bugref:9841 bugref:9746

File:

• trunk/src/VBox/VMM/VMMAll/PGMAllShw.h (modified) (8 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -33 +33 @@
 #undef SHW_PDE_ATOMIC_SET
 #undef SHW_PDE_ATOMIC_SET2
+#undef SHW_PDE_IS_BIG
 #undef SHW_PTE_PG_MASK
 #undef SHW_PTE_IS_P
@@ -69 +70 @@
 # define SHW_PD_MASK                    X86_PD_MASK
 # define SHW_TOTAL_PD_ENTRIES           X86_PG_ENTRIES
+# define SHW_PDE_IS_BIG(Pde)            ( (Pde).b.u1Size )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU32(&(Pde).u, (uNew)); } while (0)
 # define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU32(&(Pde).u, (Pde2).u); } while (0)
@@ -102 +104 @@
 # define SHW_PD_SHIFT                   EPT_PD_SHIFT
 # define SHW_PD_MASK                    EPT_PD_MASK
+# define SHW_PDE_IS_BIG(Pde)            ( (Pde).u & EPT_E_LEAF )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
 # define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
 # define SHW_PTE_PG_MASK                EPT_PTE_PG_MASK
-# define SHW_PTE_IS_P(Pte)              ( (Pte).n.u1Present )  /* Approximation, works for us. */
-# define SHW_PTE_IS_RW(Pte)             ( (Pte).n.u1Write )
+# define SHW_PTE_IS_P(Pte)              ( (Pte).u & EPT_E_READ ) /* Approximation, works for us. */
+# define SHW_PTE_IS_RW(Pte)             ( (Pte).u & EPT_E_WRITE )
 # define SHW_PTE_IS_US(Pte)             ( true )
 # define SHW_PTE_IS_A(Pte)              ( true )
 # define SHW_PTE_IS_D(Pte)              ( true )
-# define SHW_PTE_IS_P_RW(Pte)           ( (Pte).n.u1Present && (Pte).n.u1Write )
+# define SHW_PTE_IS_P_RW(Pte)           ( ((Pte).u & (EPT_E_READ | EPT_E_WRITE)) == (EPT_E_READ | EPT_E_WRITE) )
 # define SHW_PTE_IS_TRACK_DIRTY(Pte)    ( false )
-# define SHW_PTE_GET_HCPHYS(Pte)        ( (Pte).u & X86_PTE_PG_MASK )
+# define SHW_PTE_GET_HCPHYS(Pte)        ( (Pte).u & EPT_PTE_PG_MASK )
 # define SHW_PTE_LOG64(Pte)             ( (Pte).u )
 # define SHW_PTE_GET_U(Pte)             ( (Pte).u )             /**< Use with care. */
@@ -118 +121 @@
 # define SHW_PTE_ATOMIC_SET(Pte, uNew)  do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
 # define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
-# define SHW_PTE_SET_RO(Pte)            do { (Pte).n.u1Write = 0; } while (0)
-# define SHW_PTE_SET_RW(Pte)            do { (Pte).n.u1Write = 1; } while (0)
+# define SHW_PTE_SET_RO(Pte)            do { (Pte).u &= ~EPT_E_WRITE; } while (0)
+# define SHW_PTE_SET_RW(Pte)            do { (Pte).u |= EPT_E_WRITE; } while (0)
 # define SHW_PT_SHIFT                   EPT_PT_SHIFT
 # define SHW_PT_MASK                    EPT_PT_MASK
@@ -125 +128 @@
 # define SHW_PDPT_MASK                  EPT_PDPT_MASK
 # define SHW_PDPE_PG_MASK               EPT_PDPE_PG_MASK
-# define SHW_TOTAL_PD_ENTRIES           (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
+# define SHW_TOTAL_PD_ENTRIES           (EPT_PG_AMD64_ENTRIES * EPT_PG_AMD64_PDPE_ENTRIES)
 
 #else
@@ -139 +142 @@
 # define SHW_PD_SHIFT                   X86_PD_PAE_SHIFT
 # define SHW_PD_MASK                    X86_PD_PAE_MASK
+# define SHW_PDE_IS_BIG(Pde)            ( (Pde).u & X86_PDE_PS )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
 # define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
@@ -368 +372 @@
 
     /* Deal with large pages. */
-    if (Pde.b.u1Size)
+    if (SHW_PDE_IS_BIG(Pde))
     {
         /*
@@ -544 +548 @@
             return VERR_PAGE_TABLE_NOT_PRESENT;
 
-        AssertFatal(!Pde.b.u1Size);
+        AssertFatal(!SHW_PDE_IS_BIG(Pde));
 
         /*