Changeset 86464 in vbox for trunk

Timestamp:

Oct 7, 2020 8:09:22 AM (4 years ago)

Author:

vboxsync

Message:

VMM/PGMAll.h: No EPT bitfields. bugref:9841 bugref:9746

Location:

trunk

Files:

• include/VBox/vmm/hm_vmx.h (modified) (7 diffs)
• src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/PGMAllBth.h (modified) (7 diffs)
• src/VBox/VMM/VMMAll/PGMAllShw.h (modified) (6 diffs)

trunk/include/VBox/vmm/hm_vmx.h

@@ -445 +445 @@
 /** @} */
 
-/** @name VMX EPT paging structures
- * @{
- */
-
-/** @name Common bits
+/** @name VMX Extended Page Tables (EPT) Common Bits
  * @{ */
 /** Bit 0 - Readable (we often think of it as present). */
@@ -484 +480 @@
 /** Bits 3-5 - Memory type: WB. */
 #define EPT_E_TYPE_WB           (UINT64_C(6) << EPT_E_TYPE_SHIFT)
+/** Bits 3-5 - Memory type: Invalid (7). */
+#define EPT_E_TYPE_INVALID_7    (UINT64_C(7) << EPT_E_TYPE_SHIFT)
 
 /** Bit 6 - Ignore page attribute table (leaf, MBZ). */
@@ -526 +524 @@
 /** @} */
 
+
+/** @name VMX Extended Page Tables (EPT) Structures
+ * @{
+ */
+
 /**
  * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
@@ -570 +573 @@
 typedef union EPTPML4E
 {
+#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
     /** Normal view. */
     EPTPML4EBITS    n;
+#endif
     /** Unsigned integer view. */
     X86PGPAEUINT    u;
@@ -635 +640 @@
 typedef union EPTPDPTE
 {
+#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
     /** Normal view. */
     EPTPDPTEBITS    n;
+#endif
     /** Unsigned integer view. */
     X86PGPAEUINT    u;
@@ -734 +741 @@
 typedef union EPTPDE
 {
+#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
     /** Normal view. */
     EPTPDEBITS      n;
     /** 2MB view (big). */
     EPTPDE2MBITS    b;
+#endif
     /** Unsigned integer view. */
     X86PGPAEUINT    u;
@@ -808 +817 @@
 typedef union EPTPTE
 {
+#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
     /** Normal view. */
     EPTPTEBITS      n;
+#endif
     /** Unsigned integer view. */
     X86PGPAEUINT    u;

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -21 +21 @@
 *********************************************************************************************************************************/
 #define LOG_GROUP LOG_GROUP_PGM
+#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
 #include <VBox/vmm/pgm.h>
 #include <VBox/vmm/cpum.h>

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -632 +632 @@
 #  endif
     if (    !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
-        &&  !pPDDst->a[iPDDst].n.u1Present)
+        &&  !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
     {
         STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
@@ -1467 +1467 @@
         LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
 # if PGM_SHW_TYPE == PGM_TYPE_EPT
-        pPteDst->u             = PGM_PAGE_GET_HCPHYS(pPage);
-        pPteDst->n.u1Present   = 1;
-        pPteDst->n.u1Execute   = 1;
-        pPteDst->n.u1IgnorePAT = 1;
-        pPteDst->n.u3EMT       = VMX_EPT_MEMTYPE_WB;
-        /* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
+        pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) | EPT_E_READ | EPT_E_EXECUTE | EPT_E_TYPE_WB | EPT_E_IGNORE_PAT;
 # else
         if (fPteSrc & X86_PTE_A)
@@ -1496 +1491 @@
 #   if PGM_SHW_TYPE == PGM_TYPE_EPT
         /* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
-        pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
+        pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
         /* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
-        pPteDst->n.u1Present = 0;
-        pPteDst->n.u1Write   = 1;
-        pPteDst->n.u1Execute = 0;
+                   | EPT_E_WRITE
         /* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
-        pPteDst->n.u3EMT     = 7;
+                   | EPT_E_TYPE_INVALID_3;
 #   else
         /* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64).  */
@@ -1658 +1651 @@
                     STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
 # if PGM_SHW_TYPE == PGM_TYPE_EPT
-                    PteDst.u             = PGM_PAGE_GET_HCPHYS(pPage);
-                    PteDst.n.u1Present   = 1;
-                    PteDst.n.u1Write     = 1;
-                    PteDst.n.u1Execute   = 1;
-                    PteDst.n.u1IgnorePAT = 1;
-                    PteDst.n.u3EMT       = VMX_EPT_MEMTYPE_WB;
-                    /* PteDst.n.u1Size = 0 */
+                    PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
+                             | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_TYPE_WB | EPT_E_IGNORE_PAT;
 # else
                     SHW_PTE_SET(PteDst, fGstShwPteFlags | PGM_PAGE_GET_HCPHYS(pPage));
@@ -2128 +2116 @@
 #   endif
     /* In the guest SMP case we could have blocked while another VCPU reused this page table. */
-    if (!PdeDst.n.u1Present)
+    if (!SHW_PDE_IS_P(PdeDst))
     {
         AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
@@ -2136 +2124 @@
 
     /* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
-    if (PdeDst.n.u1Size)
+    if (SHW_PDE_IS_BIG(PdeDst))
     {
         Assert(pVM->pgm.s.fNestedPaging);
@@ -2993 +2981 @@
     Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
 # endif
-    Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
+    Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
 
 # if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -33 +33 @@
 #undef SHW_PDE_ATOMIC_SET
 #undef SHW_PDE_ATOMIC_SET2
+#undef SHW_PDE_IS_P
 #undef SHW_PDE_IS_BIG
 #undef SHW_PTE_PG_MASK
@@ -70 +71 @@
 # define SHW_PD_MASK                    X86_PD_MASK
 # define SHW_TOTAL_PD_ENTRIES           X86_PG_ENTRIES
+# define SHW_PDE_IS_P(Pde)              ( (Pde).n.u1Present )
 # define SHW_PDE_IS_BIG(Pde)            ( (Pde).b.u1Size )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU32(&(Pde).u, (uNew)); } while (0)
@@ -104 +106 @@
 # define SHW_PD_SHIFT                   EPT_PD_SHIFT
 # define SHW_PD_MASK                    EPT_PD_MASK
+# define SHW_PDE_IS_P(Pde)              ( (Pde).u & EPT_E_READ /* always set*/ )
 # define SHW_PDE_IS_BIG(Pde)            ( (Pde).u & EPT_E_LEAF )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
@@ -142 +145 @@
 # define SHW_PD_SHIFT                   X86_PD_PAE_SHIFT
 # define SHW_PD_MASK                    X86_PD_PAE_MASK
+# define SHW_PDE_IS_P(Pde)              ( (Pde).u & X86_PDE_P )
 # define SHW_PDE_IS_BIG(Pde)            ( (Pde).u & X86_PDE_PS )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
@@ -368 +372 @@
 #  error "Misconfigured PGM_SHW_TYPE or something..."
 # endif
-    if (!Pde.n.u1Present)
+    if (!SHW_PDE_IS_P(Pde))
         return VERR_PAGE_TABLE_NOT_PRESENT;
 
@@ -545 +549 @@
         X86PDE          Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
 # endif
-        if (!Pde.n.u1Present)
+        if (!SHW_PDE_IS_P(Pde))
             return VERR_PAGE_TABLE_NOT_PRESENT;