Index: trunk/src/VBox/VMM/include/PGMInline.h
===================================================================
--- trunk/src/VBox/VMM/include/PGMInline.h	(revision 86462)
+++ trunk/src/VBox/VMM/include/PGMInline.h	(revision 86465)
@@ -783,6 +783,5 @@
     {
         const unsigned iPdpt = (uint32_t)GCPtr >> X86_PDPT_SHIFT;
-        if (    pGuestPDPT->a[iPdpt].n.u1Present
-            &&  !(pGuestPDPT->a[iPdpt].u & pVCpu->pgm.s.fGstPaeMbzPdpeMask) )
+        if ((pGuestPDPT->a[iPdpt].u & (pVCpu->pgm.s.fGstPaeMbzPdpeMask | X86_PDPE_P)) == X86_PDPE_P)
         {
             const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
@@ -828,36 +827,37 @@
 
     /* The PDPE. */
-    PX86PDPT        pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
-    if (RT_UNLIKELY(!pGuestPDPT))
-        return NULL;
-    const unsigned  iPdpt = (uint32_t)GCPtr >> X86_PDPT_SHIFT;
-    if (pPdpe)
-        *pPdpe = pGuestPDPT->a[iPdpt];
-    if (!pGuestPDPT->a[iPdpt].n.u1Present)
-        return NULL;
-    if (RT_UNLIKELY(pVCpu->pgm.s.fGstPaeMbzPdpeMask & pGuestPDPT->a[iPdpt].u))
-        return NULL;
-
-    /* The PDE. */
+    PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
+    if (pGuestPDPT)
+    {
+        const unsigned     iPdpt = (uint32_t)GCPtr >> X86_PDPT_SHIFT;
+        X86PGPAEUINT const uPdpe = pGuestPDPT->a[iPdpt].u;
+        if (pPdpe)
+            pPdpe->u = uPdpe;
+        if ((uPdpe & (pVCpu->pgm.s.fGstPaeMbzPdpeMask | X86_PDPE_P)) == X86_PDPE_P)
+        {
+
+            /* The PDE. */
 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-    PX86PDPAE   pGuestPD = NULL;
-    int rc = pgmRZDynMapGCPageInlined(pVCpu,
-                                      pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK,
-                                      (void **)&pGuestPD
-                                      RTLOG_COMMA_SRC_POS);
-    if (RT_FAILURE(rc))
-    {
-        AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
-        return NULL;
-    }
+            PX86PDPAE   pGuestPD = NULL;
+            int rc = pgmRZDynMapGCPageInlined(pVCpu,
+                                              uPdpe & X86_PDPE_PG_MASK,
+                                              (void **)&pGuestPD
+                                              RTLOG_COMMA_SRC_POS);
+            if (RT_FAILURE(rc))
+            {
+                AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
+                return NULL;
+            }
 #else
-    PX86PDPAE   pGuestPD = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
-    if (    !pGuestPD
-        ||  (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt])
-        pgmGstLazyMapPaePD(pVCpu, iPdpt, &pGuestPD);
+            PX86PDPAE   pGuestPD = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
+            if (    !pGuestPD
+                ||  (uPdpe & X86_PDPE_PG_MASK) != pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt])
+                pgmGstLazyMapPaePD(pVCpu, iPdpt, &pGuestPD);
 #endif
-
-    *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-    return pGuestPD;
+            *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+            return pGuestPD;
+        }
+    }
+    return NULL;
 }
 
@@ -919,5 +919,7 @@
 #else
     PX86PML4 pGuestPml4 = pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4);
-    if (RT_UNLIKELY(!pGuestPml4))
+    if (pGuestPml4)
+    { /* likely */ }
+    else
     {
          int rc = pgmGstLazyMapPml4(pVCpu, &pGuestPml4);
@@ -944,28 +946,30 @@
      *       supporting 52-bit wide physical guest addresses.
      */
-    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pVCpu);
-    const unsigned  iPml4      = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
-    if (    RT_LIKELY(pGuestPml4)
-        &&  pGuestPml4->a[iPml4].n.u1Present
-        &&  !(pGuestPml4->a[iPml4].u & pVCpu->pgm.s.fGstAmd64MbzPml4eMask) )
-    {
-        PCX86PDPT   pPdptTemp;
-        int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
-        if (RT_SUCCESS(rc))
+    PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pVCpu);
+    if (RT_LIKELY(pGuestPml4))
+    {
+        const unsigned     iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
+        X86PGPAEUINT const uPml4e = pGuestPml4->a[iPml4].u;
+        if ((uPml4e & (pVCpu->pgm.s.fGstAmd64MbzPml4eMask | X86_PML4E_P)) == X86_PML4E_P)
         {
-            const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
-            if (    pPdptTemp->a[iPdpt].n.u1Present
-                &&  !(pPdptTemp->a[iPdpt].u & pVCpu->pgm.s.fGstAmd64MbzPdpeMask) )
+            PCX86PDPT pPdptTemp;
+            int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, uPml4e & X86_PML4E_PG_MASK, &pPdptTemp);
+            if (RT_SUCCESS(rc))
             {
-                PCX86PDPAE pPD;
-                rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
-                if (RT_SUCCESS(rc))
+                const unsigned     iPdpt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
+                X86PGPAEUINT const uPdpte = pPdptTemp->a[iPdpt].u;
+                if ((uPdpte & (pVCpu->pgm.s.fGstAmd64MbzPdpeMask | X86_PDPE_P)) == X86_PDPE_P)
                 {
-                    const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-                    return pPD->a[iPD];
+                    PCX86PDPAE pPD;
+                    rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, uPdpte & X86_PDPE_PG_MASK, &pPD);
+                    if (RT_SUCCESS(rc))
+                    {
+                        const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+                        return pPD->a[iPD];
+                    }
                 }
             }
+            AssertMsg(RT_SUCCESS(rc) || rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
         }
-        AssertMsg(RT_SUCCESS(rc) || rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
     }
 
@@ -989,40 +993,38 @@
 {
     /* The PMLE4. */
-    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pVCpu);
-    if (RT_UNLIKELY(!pGuestPml4))
-        return NULL;
-    const unsigned  iPml4      = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
-    PCX86PML4E      pPml4e     = *ppPml4e = &pGuestPml4->a[iPml4];
-    if (!pPml4e->n.u1Present)
-        return NULL;
-    if (RT_UNLIKELY(pPml4e->u & pVCpu->pgm.s.fGstAmd64MbzPml4eMask))
-        return NULL;
-
-    /* The PDPE. */
-    PCX86PDPT       pPdptTemp;
-    int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
-    if (RT_FAILURE(rc))
-    {
-        AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
-        return NULL;
-    }
-    const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
-    *pPdpe = pPdptTemp->a[iPdpt];
-    if (!pPdpe->n.u1Present)
-        return NULL;
-    if (RT_UNLIKELY(pPdpe->u & pVCpu->pgm.s.fGstAmd64MbzPdpeMask))
-        return NULL;
-
-    /* The PDE. */
-    PX86PDPAE pPD;
-    rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
-    if (RT_FAILURE(rc))
-    {
-        AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
-        return NULL;
-    }
-
-    *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-    return pPD;
+    PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pVCpu);
+    if (pGuestPml4)
+    {
+        const unsigned     iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
+        *ppPml4e = &pGuestPml4->a[iPml4];
+        X86PGPAEUINT const uPml4e = pGuestPml4->a[iPml4].u;
+        if ((uPml4e & (pVCpu->pgm.s.fGstAmd64MbzPml4eMask | X86_PML4E_P)) == X86_PML4E_P)
+        {
+            /* The PDPE. */
+            PCX86PDPT pPdptTemp;
+            int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, uPml4e & X86_PML4E_PG_MASK, &pPdptTemp);
+            if (RT_SUCCESS(rc))
+            {
+                const unsigned     iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
+                X86PGPAEUINT const uPdpe = pPdptTemp->a[iPdpt].u;
+                pPdpe->u = uPdpe;
+                if ((uPdpe & (pVCpu->pgm.s.fGstAmd64MbzPdpeMask | X86_PDPE_P)) == X86_PDPE_P)
+                {
+                    /* The PDE. */
+                    PX86PDPAE pPD;
+                    rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, uPdpe & X86_PDPE_PG_MASK, &pPD);
+                    if (RT_SUCCESS(rc))
+                    {
+                        *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+                        return pPD;
+                    }
+                    AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
+                }
+            }
+            else
+                AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
+        }
+    }
+    return NULL;
 }
 
@@ -1092,28 +1094,4 @@
  * @returns Pointer to the shadow PD.
  * @param   pVCpu       The cross context virtual CPU structure.
- * @param   GCPtr       The address.
- */
-DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr)
-{
-    const unsigned  iPdpt = (uint32_t)GCPtr >> X86_PDPT_SHIFT;
-    PX86PDPT        pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
-
-    if (!pPdpt->a[iPdpt].n.u1Present)
-        return NULL;
-
-    /* Fetch the pgm pool shadow descriptor. */
-    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
-    PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
-    AssertReturn(pShwPde, NULL);
-
-    return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
-}
-
-
-/**
- * Gets the shadow page directory for the specified address, PAE.
- *
- * @returns Pointer to the shadow PD.
- * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pPdpt       Pointer to the page directory pointer table.
  * @param   GCPtr       The address.
@@ -1122,14 +1100,27 @@
 {
     const unsigned  iPdpt = (uint32_t)GCPtr >> X86_PDPT_SHIFT;
-
-    if (!pPdpt->a[iPdpt].n.u1Present)
-        return NULL;
-
-    /* Fetch the pgm pool shadow descriptor. */
-    PVMCC             pVM     = pVCpu->CTX_SUFF(pVM);
-    PPGMPOOLPAGE    pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
-    AssertReturn(pShwPde, NULL);
-
-    return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
+    if (pPdpt->a[iPdpt].u & X86_PDPE_P)
+    {
+        /* Fetch the pgm pool shadow descriptor. */
+        PVMCC           pVM     = pVCpu->CTX_SUFF(pVM);
+        PPGMPOOLPAGE    pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
+        AssertReturn(pShwPde, NULL);
+
+        return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
+    }
+    return NULL;
+}
+
+
+/**
+ * Gets the shadow page directory for the specified address, PAE.
+ *
+ * @returns Pointer to the shadow PD.
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   GCPtr       The address.
+ */
+DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr)
+{
+    return pgmShwGetPaePDPtr(pVCpu, pgmShwGetPaePDPTPtr(pVCpu), GCPtr);
 }
 
@@ -1144,13 +1135,11 @@
 DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PVMCPUCC pVCpu, RTGCPTR GCPtr)
 {
-    const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-
-    PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pVCpu, GCPtr);
-    if (!pShwPde)
-    {
-        X86PDEPAE ZeroPde = {0};
-        return ZeroPde;
-    }
-    return pShwPde->a[iPd];
+    const unsigned  iPd     = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+    PX86PDPAE       pShwPde = pgmShwGetPaePDPtr(pVCpu, GCPtr);
+    if (pShwPde)
+        return pShwPde->a[iPd];
+
+    X86PDEPAE ZeroPde = {0};
+    return ZeroPde;
 }
 
@@ -1166,9 +1155,8 @@
 DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr)
 {
-    const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-
-    PX86PDPAE pPde = pgmShwGetPaePDPtr(pVCpu, GCPtr);
-    AssertReturn(pPde, NULL);
-    return &pPde->a[iPd];
+    const unsigned iPd     = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+    PX86PDPAE      pShwPde = pgmShwGetPaePDPtr(pVCpu, GCPtr);
+    AssertReturn(pShwPde, NULL);
+    return &pShwPde->a[iPd];
 }
 
@@ -1195,13 +1183,11 @@
 DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PVMCPUCC pVCpu, RTGCPTR GCPtr)
 {
-    const unsigned  iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
+    const unsigned  iPml4    = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     PX86PML4        pShwPml4 = pgmShwGetLongModePML4Ptr(pVCpu);
-
-    if (!pShwPml4)
-    {
-        X86PML4E ZeroPml4e = {0};
-        return ZeroPml4e;
-    }
-    return pShwPml4->a[iPml4];
+    if (pShwPml4)
+        return pShwPml4->a[iPml4];
+
+    X86PML4E ZeroPml4e = {0};
+    return ZeroPml4e;
 }
 
@@ -1217,7 +1203,7 @@
 {
     PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pVCpu);
-    if (!pShwPml4)
-        return NULL;
-    return &pShwPml4->a[iPml4];
+    if (pShwPml4)
+        return &pShwPml4->a[iPml4];
+    return NULL;
 }
 
