Index: trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAll.cpp	(revision 86475)
+++ trunk/src/VBox/VMM/VMMAll/PGMAll.cpp	(revision 86476)
@@ -1428,5 +1428,5 @@
                 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
                 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
-                pPde->n.u1Write = 1;
+                pPde->u |= X86_PDE_RW;
                 Log(("-> PDE=%#llx (PAE)\n", pPde->u));
                 break;
Index: trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 86475)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 86476)
@@ -467,4 +467,5 @@
      * Set the accessed and dirty flags.
      */
+/** @todo Use atomics here as we don't own the lock and stuff: */
 #   if PGM_GST_TYPE == PGM_TYPE_AMD64
     GstWalk.Pml4e.u     |= X86_PML4E_A;
@@ -475,5 +476,5 @@
     if (GstWalk.Core.fBigPage)
     {
-        Assert(GstWalk.Pde.b.u1Size);
+        Assert(GstWalk.Pde.u & X86_PDE_PS);
         if (uErr & X86_TRAP_PF_RW)
         {
@@ -489,5 +490,5 @@
     else
     {
-        Assert(!GstWalk.Pde.b.u1Size);
+        Assert(!(GstWalk.Pde.u & X86_PDE_PS));
         GstWalk.Pde.u   |= X86_PDE_A;
         GstWalk.pPde->u |= X86_PDE_A;
@@ -629,5 +630,5 @@
      */
 #  if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
-    Assert(GstWalk.Pde.n.u1Present);
+    Assert(GstWalk.Pde.u & X86_PDE_P);
 #  endif
     if (    !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
@@ -835,5 +836,5 @@
                 if (   GstWalk.Core.fEffectiveUS
                     && !GstWalk.Core.fEffectiveRW
-                    && (GstWalk.Core.fBigPage || GstWalk.Pde.n.u1Write)
+                    && (GstWalk.Core.fBigPage || (GstWalk.Pde.u & X86_PDE_RW))
                     && pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
                 {
@@ -918,5 +919,5 @@
         else if (    GstWalk.Core.fEffectiveUS
                  && !GstWalk.Core.fEffectiveRW
-                 && (GstWalk.Core.fBigPage || GstWalk.Pde.n.u1Write)
+                 && (GstWalk.Core.fBigPage || (GstWalk.Pde.u & X86_PDE_RW))
                  &&  pVCpu->pgm.s.cNetwareWp0Hacks > 0
                  &&  (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP | X86_CR0_PG)) == X86_CR0_PG
@@ -1117,5 +1118,5 @@
 
     const SHWPDE PdeDst = *pPdeDst;
-    if (!PdeDst.n.u1Present)
+    if (!(PdeDst.u & X86_PDE_P))
     {
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
@@ -1149,5 +1150,5 @@
 # endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
     const bool      fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
-    const bool      fIsBigPage  = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
+    const bool      fIsBigPage  = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
     if (fWasBigPage != fIsBigPage)
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
@@ -1163,5 +1164,5 @@
         || (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
             && fIsBigPage
-            && PdeSrc.b.u1Global
+            && (PdeSrc.u & X86_PDE4M_G)
            )
        )
@@ -1179,8 +1180,8 @@
      */
     rc = VINF_SUCCESS;
-    if (PdeSrc.n.u1Present)
-    {
-        Assert(     PdeSrc.n.u1User == PdeDst.n.u1User
-               &&   (PdeSrc.n.u1Write || !PdeDst.n.u1Write || pVCpu->pgm.s.cNetwareWp0Hacks > 0));
+    if (PdeSrc.u & X86_PDE_P)
+    {
+        Assert(    (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
+               &&  ((PdeSrc.u & X86_PDE_RW) || !(PdeDst.u & X86_PDE_RW) || pVCpu->pgm.s.cNetwareWp0Hacks > 0));
 # ifndef PGM_WITHOUT_MAPPINGS
         if (PdeDst.u & PGM_PDFLAGS_MAPPING)
@@ -1264,5 +1265,5 @@
                 if (        (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US))
                         ==  (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US))
-                    &&  (   PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
+                    &&  (   (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
                          || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
                 {
@@ -1615,5 +1616,5 @@
                  * we mark the page not present.
                  */
-                if (!PteSrc.n.u1Accessed || !PdeSrc.n.u1Accessed)
+                if (!(PteSrc.u & X86_PTE_A) || !(PdeSrc.u & X86_PDE_A))
                 {
                     LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
@@ -1625,6 +1626,7 @@
                  * when the page is modified.
                  */
-                else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
+                else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
                 {
+                    AssertCompile(X86_PTE_RW == X86_PDE_RW);
                     STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
                     SHW_PTE_SET(PteDst,
@@ -1747,5 +1749,5 @@
      * Assert preconditions.
      */
-    Assert(PdeSrc.n.u1Present);
+    Assert(PdeSrc.u & X86_PDE_P);
     Assert(cPages);
 #  if 0 /* rarely useful; leave for debugging. */
@@ -1798,5 +1800,5 @@
      *   the modified entry, we may end up here with a "stale" TLB entry.
      */
-    if (!PdeDst.n.u1Present)
+    if (!(PdeDst.u & X86_PDE_P))
     {
         Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
@@ -1820,5 +1822,5 @@
      * Check that the page is present and that the shadow PDE isn't out of sync.
      */
-    const bool      fBigPage  = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
+    const bool      fBigPage  = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
     const bool      fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
     RTGCPHYS        GCPhys;
@@ -1840,11 +1842,11 @@
     }
     /** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
-    if (    fPdeValid
-        &&  pShwPage->GCPhys == GCPhys
-        &&  PdeSrc.n.u1Present
-        &&  PdeSrc.n.u1User == PdeDst.n.u1User
-        &&  (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
+    if (   fPdeValid
+        && pShwPage->GCPhys == GCPhys
+        && (PdeSrc.u & X86_PDE_P)
+        && (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
+        && ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) || !(PdeDst.u & X86_PDE_RW))
 #  if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
-        &&  (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !GST_IS_NX_ACTIVE(pVCpu))
+        && ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) || !GST_IS_NX_ACTIVE(pVCpu))
 #  endif
        )
@@ -1855,5 +1857,5 @@
          * check is only meant for dealing with non-#PF'ing paths.
          */
-        if (PdeSrc.n.u1Accessed)
+        if (PdeSrc.u & X86_PDE_A)
         {
             PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
@@ -1954,5 +1956,5 @@
                     if (    PGM_PAGE_GET_TYPE(pPage)  == PGMPAGETYPE_RAM
                         &&  (   PGM_PAGE_IS_ZERO(pPage)
-                             || (   PdeSrc.n.u1Write
+                             || (   (PdeSrc.u & X86_PDE_RW)
                                  && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
 #   ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
@@ -2008,15 +2010,14 @@
                      * As for invlpg, it simply frees the whole shadow PT.
                      * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
-                    if (    !PdeSrc.b.u1Dirty
-                        &&  PdeSrc.b.u1Write)
+                    if ((PdeSrc.u & (X86_PDE4M_D | X86_PDE_RW)) == X86_PDE_RW)
                     {
                         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
                         PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
-                        PdeDst.n.u1Write = 0;
+                        PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
                     }
                     else
                     {
-                        PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
-                        PdeDst.n.u1Write = PdeSrc.n.u1Write;
+                        PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY | X86_PDE_RW);
+                        PdeDst.u |= PdeSrc.u & X86_PDE_RW;
                     }
                     SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
@@ -2283,20 +2284,16 @@
      * Handle big page.
      */
-    if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
-    {
-        if (    pPdeDst->n.u1Present
-            &&  (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
-        {
+    if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
+    {
+        if ((pPdeSrc->u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
+        {
+            STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
+            Assert(pPdeSrc->u & X86_PDE_RW);
+
+            /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
+             *       fault again and take this path to only invalidate the entry (see below). */
             SHWPDE PdeDst = *pPdeDst;
-
-            STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
-            Assert(pPdeSrc->b.u1Write);
-
-            /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
-             *       fault again and take this path to only invalidate the entry (see below).
-             */
-            PdeDst.n.u1Write      = 1;
-            PdeDst.n.u1Accessed   = 1;
-            PdeDst.au32[0]       &= ~PGM_PDFLAGS_TRACK_DIRTY;
+            PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
+            PdeDst.u |= X86_PDE_RW | X86_PDE_A;
             SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
             PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
@@ -2306,7 +2303,6 @@
 # ifdef IN_RING0
         /* Check for stale TLB entry; only applies to the SMP guest case. */
-        if (    pVM->cCpus > 1
-            &&  pPdeDst->n.u1Write
-            &&  pPdeDst->n.u1Accessed)
+        if (   pVM->cCpus > 1
+            && (pPdeDst->u & (X86_PDE_P | X86_PDE_RW | X86_PDE_A)) == (X86_PDE_P | X86_PDE_RW | X86_PDE_A))
         {
             PPGMPOOLPAGE    pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
@@ -2333,11 +2329,7 @@
     PGSTPT pPTSrc;
     int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
-    if (RT_FAILURE(rc))
-    {
-        AssertRC(rc);
-        return rc;
-    }
-
-    if (pPdeDst->n.u1Present)
+    AssertRCReturn(rc, rc);
+
+    if (SHW_PDE_IS_P(*pPdeDst))
     {
         GSTPTE const  *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
@@ -2551,5 +2543,5 @@
     }
 # endif /* !PGM_WITHOUT_MAPPINGS */
-    Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
+    Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
 
     /*
@@ -2557,6 +2549,6 @@
      */
     GSTPDE      PdeSrc = pPDSrc->a[iPDSrc];
-    const bool  fPageTable = !PdeSrc.b.u1Size || !GST_IS_PSE_ACTIVE(pVCpu);
-    if (   PdeSrc.n.u1Present
+    const bool  fPageTable = !(PdeSrc.u & X86_PDE_PS) || !GST_IS_PSE_ACTIVE(pVCpu);
+    if (   (PdeSrc.u & X86_PDE_P)
         && (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
     {
@@ -2582,5 +2574,5 @@
             PGMPOOLACCESS enmAccess;
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
-            const bool  fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
+            const bool  fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
 # else
             const bool  fNoExecute = false;
@@ -2593,7 +2585,7 @@
 # endif
             /* Determine the right kind of large page to avoid incorrect cached entry reuse. */
-            if (PdeSrc.n.u1User)
+            if (PdeSrc.u & X86_PDE_US)
             {
-                if (PdeSrc.n.u1Write)
+                if (PdeSrc.u & X86_PDE_RW)
                     enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
                 else
@@ -2602,5 +2594,5 @@
             else
             {
-                if (PdeSrc.n.u1Write)
+                if (PdeSrc.u & X86_PDE_RW)
                     enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
                 else
@@ -2624,10 +2616,9 @@
                 PdeDst.u = pShwPage->Core.Key | GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
                 /* (see explanation and assumptions further down.) */
-                if (    !PdeSrc.b.u1Dirty
-                    &&  PdeSrc.b.u1Write)
+                if ((PdeSrc.u & (X86_PDE_RW | X86_PDE4M_D)) == X86_PDE_RW)
                 {
                     STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
                     PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
-                    PdeDst.b.u1Write = 0;
+                    PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
                 }
             }
@@ -2655,5 +2646,5 @@
          * The best idea is to leave this change to the caller and add an
          * assertion that it's set already. */
-        pPDSrc->a[iPDSrc].n.u1Accessed = 1;
+        pPDSrc->a[iPDSrc].u |= X86_PDE_A;
         if (fPageTable)
         {
@@ -2763,10 +2754,9 @@
             /** @todo move the above stuff to a section in the PGM documentation. */
             Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
-            if (    !PdeSrc.b.u1Dirty
-                &&  PdeSrc.b.u1Write)
+            if ((PdeSrc.u & (X86_PDE_RW | X86_PDE4M_D)) == X86_PDE_RW)
             {
                 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
                 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
-                PdeDst.b.u1Write = 0;
+                PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
             }
             SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
@@ -2890,5 +2880,5 @@
     }
     else
-        AssertRelease(!PdeDst.n.u1Present);
+        AssertRelease(!SHW_PDE_IS_P(PdeDst));
 
     STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
@@ -3029,10 +3019,6 @@
                          | (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
 #  else
-                PdeDst.u &= X86_PDE_AVL_MASK;
-                PdeDst.n.u1Present   = 1;
-                PdeDst.n.u1Write     = 1;
-                PdeDst.b.u1Size      = 1;
-                PdeDst.n.u1User      = 1;
-                PdeDst.u |= HCPhys; /* Note! Must be done last of gcc v10.2.1 20200723 (Red Hat 10.2.1-1) may drop the top 32 bits. */
+                PdeDst.u = HCPhys | X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PS
+                         | (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
 #  endif
                 SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
@@ -3101,11 +3087,6 @@
              | (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
 # else
-    PdeDst.u &= X86_PDE_AVL_MASK;
-    PdeDst.n.u1Present  = 1;
-    PdeDst.n.u1Write    = 1;
-    PdeDst.n.u1User     = 1;
-    PdeDst.n.u1Accessed = 1;
-    PdeDst.u |= pShwPage->Core.Key; /* Note! Must be done last of gcc v10.2.1 20200723 (Red Hat 10.2.1-1) drops the top 32 bits. */
-    /** @todo r=bird: Stop using bitfields.  But we need to defined/find the EPT flags then. */
+    PdeDst.u = pShwPage->Core.Key | X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A
+             | (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
 # endif
     SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
@@ -3171,14 +3152,8 @@
     PGSTPD          pPDSrc = NULL;
     const unsigned  iPDSrc = 0;
-    GSTPDE          PdeSrc;
-
-    PdeSrc.u            = 0; /* faked so we don't have to #ifdef everything */
-    PdeSrc.n.u1Present  = 1;
-    PdeSrc.n.u1Write    = 1;
-    PdeSrc.n.u1Accessed = 1;
-    PdeSrc.n.u1User     = 1;
-# endif
-
-    if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
+    GSTPDE const    PdeSrc = { X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A }; /* faked so we don't have to #ifdef everything */
+# endif
+
+    if ((PdeSrc.u & (X86_PDE_P | X86_PDE_A)) == (X86_PDE_P | X86_PDE_A))
     {
         PVMCC pVM = pVCpu->CTX_SUFF(pVM);
@@ -3237,5 +3212,5 @@
 # endif
         {
-            if (!PdeDst.n.u1Present)
+            if (!(PdeDst.u & X86_PDE_P))
             {
                 /** @todo r=bird: This guy will set the A bit on the PDE,
@@ -3386,5 +3361,5 @@
 # endif
 
-    if (!pPdeDst->n.u1Present)
+    if (!(pPdeDst->u & X86_PDE_P))
     {
         rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
@@ -3409,10 +3384,5 @@
         GSTPDE PdeSrc       = pPDSrc->a[iPDSrc];
 # else
-        GSTPDE PdeSrc;
-        PdeSrc.u            = 0; /* faked so we don't have to #ifdef everything */
-        PdeSrc.n.u1Present  = 1;
-        PdeSrc.n.u1Write    = 1;
-        PdeSrc.n.u1Accessed = 1;
-        PdeSrc.n.u1User     = 1;
+        GSTPDE const PdeSrc = { X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A }; /* faked so we don't have to #ifdef everything */
 # endif
 
@@ -3809,5 +3779,5 @@
 
                     const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
-                    if (!PdeSrc.n.u1Present)
+                    if (!(PdeSrc.u & X86_PDE_P))
                     {
                         AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
@@ -3817,6 +3787,6 @@
                     }
 
-                    if (    !PdeSrc.b.u1Size
-                        ||  !fBigPagesSupported)
+                    if (   !(PdeSrc.u & X86_PDE_PS)
+                        || !fBigPagesSupported)
                     {
                         GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
@@ -3842,6 +3812,6 @@
                     }
 
-                    if (    pPoolPage->enmKind
-                        !=  (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
+                    if (   pPoolPage->enmKind
+                        != (!(PdeSrc.u & X86_PDE_PS) || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
                     {
                         AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
@@ -3867,5 +3837,5 @@
                     }
 
-                    if (    !PdeSrc.b.u1Size
+                    if (    !(PdeSrc.u & X86_PDE_PS)
                         ||  !fBigPagesSupported)
                     {
@@ -4100,7 +4070,7 @@
                         */
                         uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | GST_PDE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
-                        if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
+                        if ((PdeSrc.u & (X86_PDE_RW | X86_PDE4M_D)) == X86_PDE_RW)
                         {
-                            if (PdeDst.n.u1Write)
+                            if (PdeDst.u & X86_PDE_RW)
                             {
                                 AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
@@ -4131,5 +4101,5 @@
                         {
                             /* access bit emulation (not implemented). */
-                            if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present)
+                            if ((PdeSrc.u & X86_PDE_A) || SHW_PDE_IS_P(PdeDst))
                             {
                                 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
@@ -4138,5 +4108,5 @@
                                 continue;
                             }
-                            if (!PdeDst.n.u1Accessed)
+                            if (!SHW_PDE_IS_A(PdeDst))
                             {
                                 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
Index: trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllGst.h	(revision 86475)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllGst.h	(revision 86476)
@@ -208,7 +208,7 @@
         GSTPDE  Pde;
         pWalk->Pde.u = Pde.u = pPde->u;
-        if (Pde.n.u1Present) { /* probable */ }
+        if (Pde.u & X86_PDE_P) { /* probable */ }
         else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
-        if (Pde.n.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
+        if ((Pde.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
         {
             if (RT_LIKELY(GST_IS_BIG_PDE_VALID(pVCpu, Pde))) { /* likely */ }
Index: trunk/src/VBox/VMM/VMMAll/PGMAllShw.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllShw.h	(revision 86475)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllShw.h	(revision 86476)
@@ -20,4 +20,5 @@
 *   Defined Constants And Macros                                                                                                 *
 *********************************************************************************************************************************/
+#undef SHWUINT
 #undef SHWPT
 #undef PSHWPT
@@ -34,4 +35,5 @@
 #undef SHW_PDE_ATOMIC_SET2
 #undef SHW_PDE_IS_P
+#undef SHW_PDE_IS_A
 #undef SHW_PDE_IS_BIG
 #undef SHW_PTE_PG_MASK
@@ -59,4 +61,5 @@
 
 #if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
+# define SHWUINT                        uint32_t
 # define SHWPT                          X86PT
 # define PSHWPT                         PX86PT
@@ -72,4 +75,5 @@
 # define SHW_TOTAL_PD_ENTRIES           X86_PG_ENTRIES
 # define SHW_PDE_IS_P(Pde)              ( (Pde).n.u1Present )
+# define SHW_PDE_IS_A(Pde)              ( (Pde).n.u1Accessed )
 # define SHW_PDE_IS_BIG(Pde)            ( (Pde).b.u1Size )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU32(&(Pde).u, (uNew)); } while (0)
@@ -95,4 +99,5 @@
 
 #elif PGM_SHW_TYPE == PGM_TYPE_EPT
+# define SHWUINT                        uint64_t
 # define SHWPT                          EPTPT
 # define PSHWPT                         PEPTPT
@@ -107,4 +112,5 @@
 # define SHW_PD_MASK                    EPT_PD_MASK
 # define SHW_PDE_IS_P(Pde)              ( (Pde).u & EPT_E_READ /* always set*/ )
+# define SHW_PDE_IS_A(Pde)              ( 1 ) /* We don't use EPT_E_ACCESSED, use with care! */
 # define SHW_PDE_IS_BIG(Pde)            ( (Pde).u & EPT_E_LEAF )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
@@ -134,4 +140,5 @@
 
 #else
+# define SHWUINT                        uint64_t
 # define SHWPT                          PGMSHWPTPAE
 # define PSHWPT                         PPGMSHWPTPAE
@@ -146,4 +153,5 @@
 # define SHW_PD_MASK                    X86_PD_PAE_MASK
 # define SHW_PDE_IS_P(Pde)              ( (Pde).u & X86_PDE_P )
+# define SHW_PDE_IS_A(Pde)              ( (Pde).u & X86_PDE_A )
 # define SHW_PDE_IS_BIG(Pde)            ( (Pde).u & X86_PDE_PS )
 # define SHW_PDE_ATOMIC_SET(Pde, uNew)  do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
