Changeset 86489 in vbox for trunk/src/VBox

Timestamp:

Oct 8, 2020 9:11:54 AM (4 years ago)

Author:

vboxsync

Message:

VMM/PGM: Working on eliminating page table bitfield use (32-bit PTEs). bugref:9841 bugref:9746

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/PGMAllPool.cpp (modified) (9 diffs)
• VMMAll/PGMAllShw.h (modified) (3 diffs)
• VMMR3/PGMPool.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -207 +207 @@
                 const unsigned iShw = off / sizeof(X86PTE);
                 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
-                if (uShw.pPT->a[iShw].n.u1Present)
+                X86PGUINT const uPde = uShw.pPT->a[iShw].u;
+                if (uPde & X86_PTE_P)
                 {
                     X86PTE GstPte;
-
                     int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
                     AssertRC(rc);
-                    Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
-                    pgmPoolTracDerefGCPhysHint(pPool, pPage,
-                                               uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
-                                               GstPte.u & X86_PTE_PG_MASK,
-                                               iShw);
+                    Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uPde & X86_PTE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
+                    pgmPoolTracDerefGCPhysHint(pPool, pPage, uPde & X86_PTE_PG_MASK, GstPte.u & X86_PTE_PG_MASK, iShw);
                     ASMAtomicWriteU32(&uShw.pPT->a[iShw].u, 0);
                 }
@@ -1595 +1592 @@
     {
         /* Check the new value written by the guest. If present and with a bogus physical address, then
-         * it's fairly safe to assume the guest is reusing the PT.
-         */
-        if (    fAllowRemoval
-            &&  pGstPT->a[i].n.u1Present)
-        {
-            if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK))
+         * it's fairly safe to assume the guest is reusing the PT. */
+        if (fAllowRemoval)
+        {
+            X86PGUINT const uPte = pGstPT->a[i].u;
+            if (   (uPte & X86_PTE_P)
+                && !PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), uPte & X86_PTE_PG_MASK))
             {
                 *pfFlush = true;
@@ -3211 +3208 @@
             if ((pPT->a[iPte].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
             {
+                Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
                 X86PTE Pte;
-
-                Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
                 Pte.u = (pPT->a[iPte].u & u32AndMask) | u32OrMask;
                 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
-                    Pte.n.u1Write = 0;    /* need to disallow writes when dirty bit tracking is still active. */
-
+                    Pte.u &= ~(X86PGUINT)X86_PTE_RW; /* need to disallow writes when dirty bit tracking is still active. */
                 ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
                 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
@@ -3638 +3633 @@
                     PX86PT          pPT      = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
                     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
-                        if (pPT->a[i].n.u1Present)
+                    {
+                        const X86PGUINT uPte = pPT->a[i].u;
+                        if (uPte & X86_PTE_P)
                         {
-                            if ((pPT->a[i].u & X86_PTE_PG_MASK) == u32)
+                            if ((uPte & X86_PTE_PG_MASK) == u32)
                             {
                                 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
-                                pPT->a[i].u = 0;
+                                ASMAtomicWriteU32(&pPT->a[i].u, 0);
 
                                 /* Update the counter as we're removing references. */
@@ -3654 +3651 @@
                                 break;
                         }
+                    }
                     PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
                     break;
@@ -3672 +3670 @@
                             {
                                 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
-                                PGMSHWPTEPAE_SET(pPT->a[i], 0); /// @todo why not atomic?
+                                PGMSHWPTEPAE_ATOMIC_SET(pPT->a[i], 0); /// @todo why not atomic?
 
                                 /* Update the counter as we're removing references. */
@@ -3699 +3697 @@
                             {
                                 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
-                                pPT->a[i].u = 0;
+                                ASMAtomicWriteU64(&pPT->a[i].u, 0);
 
                                 /* Update the counter as we're removing references. */
@@ -4320 +4318 @@
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
     {
-        Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
-        if (pShwPT->a[i].n.u1Present)
+        const X86PGUINT uPte = pShwPT->a[i].u;
+        Assert(!(uPte & RT_BIT_32(10)));
+        if (uPte & X86_PTE_P)
         {
             Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
-                  i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
-            pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
+                  i, uPte & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
+            pgmPoolTracDerefGCPhysHint(pPool, pPage, uPte & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
             if (!pPage->cPresent)
                 break;
@@ -4400 +4399 @@
     for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
     {
-        Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
-        if (pShwPT->a[i].n.u1Present)
+        const X86PGUINT uPte = pShwPT->a[i].u;
+        Assert(!(uPte & RT_BIT_32(10)));
+        if (uPte & X86_PTE_P)
         {
             Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
-                  i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
-            pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
+                  i, uPte & X86_PTE_PG_MASK, GCPhys));
+            pgmPoolTracDerefGCPhys(pPool, pPage, uPte & X86_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
             if (!pPage->cPresent)
                 break;

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -80 +80 @@
 # define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU32(&(Pde).u, (Pde2).u); } while (0)
 # define SHW_PTE_PG_MASK                X86_PTE_PG_MASK
-# define SHW_PTE_IS_P(Pte)              ( (Pte).n.u1Present )
-# define SHW_PTE_IS_RW(Pte)             ( (Pte).n.u1Write )
-# define SHW_PTE_IS_US(Pte)             ( (Pte).n.u1User )
-# define SHW_PTE_IS_A(Pte)              ( (Pte).n.u1Accessed )
-# define SHW_PTE_IS_D(Pte)              ( (Pte).n.u1Dirty )
-# define SHW_PTE_IS_P_RW(Pte)           ( (Pte).n.u1Present && (Pte).n.u1Write )
+# define SHW_PTE_IS_P(Pte)              ( (Pte).u & X86_PTE_P )
+# define SHW_PTE_IS_RW(Pte)             ( (Pte).u & X86_PTE_RW )
+# define SHW_PTE_IS_US(Pte)             ( (Pte).u & X86_PTE_US )
+# define SHW_PTE_IS_A(Pte)              ( (Pte).u & X86_PTE_A )
+# define SHW_PTE_IS_D(Pte)              ( (Pte).u & X86_PTE_D )
+# define SHW_PTE_IS_P_RW(Pte)           ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
 # define SHW_PTE_IS_TRACK_DIRTY(Pte)    ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
 # define SHW_PTE_GET_HCPHYS(Pte)        ( (Pte).u & X86_PTE_PG_MASK )
@@ -93 +93 @@
 # define SHW_PTE_ATOMIC_SET(Pte, uNew)  do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
 # define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
-# define SHW_PTE_SET_RO(Pte)            do { (Pte).n.u1Write = 0; } while (0)
-# define SHW_PTE_SET_RW(Pte)            do { (Pte).n.u1Write = 1; } while (0)
+# define SHW_PTE_SET_RO(Pte)            do { (Pte).u &= ~(X86PGUINT)X86_PTE_RW; } while (0)
+# define SHW_PTE_SET_RW(Pte)            do { (Pte).u |= X86_PTE_RW; } while (0)
 # define SHW_PT_SHIFT                   X86_PT_SHIFT
 # define SHW_PT_MASK                    X86_PT_MASK
@@ -130 +130 @@
 # define SHW_PTE_ATOMIC_SET(Pte, uNew)  do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
 # define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
-# define SHW_PTE_SET_RO(Pte)            do { (Pte).u &= ~EPT_E_WRITE; } while (0)
+# define SHW_PTE_SET_RO(Pte)            do { (Pte).u &= ~(uint64_t)EPT_E_WRITE; } while (0)
 # define SHW_PTE_SET_RW(Pte)            do { (Pte).u |= EPT_E_WRITE; } while (0)
 # define SHW_PT_SHIFT                   EPT_PT_SHIFT

trunk/src/VBox/VMM/VMMR3/PGMPool.cpp

@@ -793 +793 @@
                 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
                     for (unsigned iShw = 0; iShw < RT_ELEMENTS(uShw.pPT->a); iShw++)
-                    {
-                        if (uShw.pPT->a[iShw].n.u1Present)
-                            uShw.pPT->a[iShw].n.u1Write = 0;
-                    }
+                        if (uShw.pPT->a[iShw].u & X86_PTE_P)
+                            uShw.pPT->a[iShw].u = ~(X86PGUINT)X86_PTE_RW;
                     break;
 
@@ -805 +803 @@
                 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
                     for (unsigned iShw = 0; iShw < RT_ELEMENTS(uShw.pPTPae->a); iShw++)
-                    {
                         if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
                             PGMSHWPTEPAE_SET_RO(uShw.pPTPae->a[iShw]);
-                    }
                     break;
 
                 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
                     for (unsigned iShw = 0; iShw < RT_ELEMENTS(uShw.pPTEpt->a); iShw++)
-                    {
                         if (uShw.pPTEpt->a[iShw].u & EPT_E_READ)
                             uShw.pPTEpt->a[iShw].u &= ~(X86PGPAEUINT)EPT_E_WRITE;
-                    }
                     break;