Changeset 87171 in vbox for trunk/include/iprt

Timestamp:

Jan 4, 2021 9:35:43 PM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

142100

Message:

iprt/asm.h: Generic memory barriers, writes and reads. Additions, subtration, incrementing and decrementing. bugref:9898 bugref:9026

File:

• trunk/include/iprt/asm.h (modified) (39 diffs)

trunk/include/iprt/asm.h

@@ -1875 +1875 @@
 #elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
     /* Note! Only armv7 and later. */
-    __asm__ __volatile__ ("dsb sy\n\t" ::: "memory");
+    __asm__ __volatile__ ("dsb sy\n\t" ::: "memory"); /** @todo dmb? */
 #elif ARCH_BITS == 16
     uint16_t volatile u16;
@@ -1906 +1906 @@
 #elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
     /* Note! Only armv7 and later. */
-    __asm__ __volatile__ ("dmb sy\n\t" ::: "memory");
+    __asm__ __volatile__ ("dmb st\n\t" ::: "memory");
 #else
     ASMMemoryFence();
@@ -1933 +1933 @@
 #elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
     /* Note! Only armv7 and later. */
-    __asm__ __volatile__ ("dmb sy\n\t";
+    __asm__ __volatile__ ("dmb ld\n\t" ::: "memory");
 #else
     ASMMemoryFence();
@@ -1998 +1998 @@
 DECLINLINE(uint16_t) ASMAtomicReadU16(volatile uint16_t RT_FAR *pu16) RT_NOTHROW_DEF
 {
+    Assert(!((uintptr_t)pu16 & 1));
     ASMMemoryFence();
+    return *pu16;
+}
+
+
+/**
+ * Atomically reads an unsigned 16-bit value, unordered.
+ *
+ * @returns Current *pu16 value
+ * @param   pu16    Pointer to the 16-bit variable to read.
+ */
+DECLINLINE(uint16_t) ASMAtomicUoReadU16(volatile uint16_t RT_FAR *pu16) RT_NOTHROW_DEF
+{
     Assert(!((uintptr_t)pu16 & 1));
     return *pu16;
@@ -2005 +2018 @@
 
 /**
- * Atomically reads an unsigned 16-bit value, unordered.
- *
- * @returns Current *pu16 value
- * @param   pu16    Pointer to the 16-bit variable to read.
- */
-DECLINLINE(uint16_t) ASMAtomicUoReadU16(volatile uint16_t RT_FAR *pu16) RT_NOTHROW_DEF
-{
-    Assert(!((uintptr_t)pu16 & 1));
-    return *pu16;
-}
-
-
-/**
  * Atomically reads a signed 16-bit value, ordered.
  *
@@ -2025 +2025 @@
 DECLINLINE(int16_t) ASMAtomicReadS16(volatile int16_t RT_FAR *pi16) RT_NOTHROW_DEF
 {
+    Assert(!((uintptr_t)pi16 & 1));
     ASMMemoryFence();
+    return *pi16;
+}
+
+
+/**
+ * Atomically reads a signed 16-bit value, unordered.
+ *
+ * @returns Current *pi16 value
+ * @param   pi16    Pointer to the 16-bit variable to read.
+ */
+DECLINLINE(int16_t) ASMAtomicUoReadS16(volatile int16_t RT_FAR *pi16) RT_NOTHROW_DEF
+{
     Assert(!((uintptr_t)pi16 & 1));
     return *pi16;
@@ -2032 +2045 @@
 
 /**
- * Atomically reads a signed 16-bit value, unordered.
- *
- * @returns Current *pi16 value
- * @param   pi16    Pointer to the 16-bit variable to read.
- */
-DECLINLINE(int16_t) ASMAtomicUoReadS16(volatile int16_t RT_FAR *pi16) RT_NOTHROW_DEF
-{
-    Assert(!((uintptr_t)pi16 & 1));
-    return *pi16;
-}
-
-
-/**
  * Atomically reads an unsigned 32-bit value, ordered.
  *
@@ -2052 +2052 @@
 DECLINLINE(uint32_t) ASMAtomicReadU32(volatile uint32_t RT_FAR *pu32) RT_NOTHROW_DEF
 {
+    Assert(!((uintptr_t)pu32 & 3));
     ASMMemoryFence();
+#if ARCH_BITS == 16
+    AssertFailed();  /** @todo 16-bit */
+#endif
+    return *pu32;
+}
+
+
+/**
+ * Atomically reads an unsigned 32-bit value, unordered.
+ *
+ * @returns Current *pu32 value
+ * @param   pu32    Pointer to the 32-bit variable to read.
+ */
+DECLINLINE(uint32_t) ASMAtomicUoReadU32(volatile uint32_t RT_FAR *pu32) RT_NOTHROW_DEF
+{
     Assert(!((uintptr_t)pu32 & 3));
 #if ARCH_BITS == 16
@@ -2062 +2078 @@
 
 /**
- * Atomically reads an unsigned 32-bit value, unordered.
- *
- * @returns Current *pu32 value
- * @param   pu32    Pointer to the 32-bit variable to read.
- */
-DECLINLINE(uint32_t) ASMAtomicUoReadU32(volatile uint32_t RT_FAR *pu32) RT_NOTHROW_DEF
-{
-    Assert(!((uintptr_t)pu32 & 3));
+ * Atomically reads a signed 32-bit value, ordered.
+ *
+ * @returns Current *pi32 value
+ * @param   pi32    Pointer to the 32-bit variable to read.
+ */
+DECLINLINE(int32_t) ASMAtomicReadS32(volatile int32_t RT_FAR *pi32) RT_NOTHROW_DEF
+{
+    Assert(!((uintptr_t)pi32 & 3));
+    ASMMemoryFence();
 #if ARCH_BITS == 16
     AssertFailed();  /** @todo 16-bit */
 #endif
-    return *pu32;
-}
-
-
-/**
- * Atomically reads a signed 32-bit value, ordered.
+    return *pi32;
+}
+
+
+/**
+ * Atomically reads a signed 32-bit value, unordered.
  *
  * @returns Current *pi32 value
  * @param   pi32    Pointer to the 32-bit variable to read.
  */
-DECLINLINE(int32_t) ASMAtomicReadS32(volatile int32_t RT_FAR *pi32) RT_NOTHROW_DEF
-{
-    ASMMemoryFence();
+DECLINLINE(int32_t) ASMAtomicUoReadS32(volatile int32_t RT_FAR *pi32) RT_NOTHROW_DEF
+{
     Assert(!((uintptr_t)pi32 & 3));
 #if ARCH_BITS == 16
@@ -2095 +2111 @@
 
 /**
- * Atomically reads a signed 32-bit value, unordered.
- *
- * @returns Current *pi32 value
- * @param   pi32    Pointer to the 32-bit variable to read.
- */
-DECLINLINE(int32_t) ASMAtomicUoReadS32(volatile int32_t RT_FAR *pi32) RT_NOTHROW_DEF
-{
-    Assert(!((uintptr_t)pi32 & 3));
-#if ARCH_BITS == 16
-    AssertFailed();  /** @todo 16-bit */
-#endif
-    return *pi32;
-}
-
-
-/**
  * Atomically reads an unsigned 64-bit value, ordered.
  *
@@ -2120 +2120 @@
  * @remarks x86: Requires a Pentium or later.
  */
-#if (RT_INLINE_ASM_EXTERNAL && !defined(RT_ARCH_AMD64)) \
+#if (RT_INLINE_ASM_EXTERNAL_TMP_ARM && !defined(RT_ARCH_AMD64)) \
  || RT_INLINE_DONT_MIX_CMPXCHG8B_AND_PIC
 RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMAtomicReadU64(volatile uint64_t RT_FAR *pu64) RT_NOTHROW_PROTO;
@@ -2145 +2145 @@
     ASMMemoryFence();
     u64 = *pu64;
-# else /* !RT_ARCH_AMD64 */
+
+# elif defined(RT_ARCH_X86)
 #  if RT_INLINE_ASM_GNU_STYLE
 #   if defined(PIC) || defined(__PIC__)
@@ -2185 +2186 @@
     }
 #  endif
-# endif /* !RT_ARCH_AMD64 */
+
+# elif defined(RT_ARCH_ARM64)
+    Assert(!((uintptr_t)pu64 & 7));
+    ASMMemoryFence();
+    u64 = *pu64;
+
+# elif defined(RT_ARCH_ARM32)
+    Assert(!((uintptr_t)pu64 & 7));
+    __asm__ __volatile__("dsb sy\n\t" /** @todo dmb? */
+                         "ldrexd    %0, %H0, [%1]\n\t"
+                         : "=&r" (u64)
+                         : "r" (pu64)
+                         : "memory");
+
+# else
+#  error "Port me"
+# endif
     return u64;
 }
@@ -2202 +2219 @@
  */
 #if !defined(RT_ARCH_AMD64) \
-  && (   (RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN) \
+  && (   (RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN) \
       || RT_INLINE_DONT_MIX_CMPXCHG8B_AND_PIC)
 RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMAtomicUoReadU64(volatile uint64_t RT_FAR *pu64) RT_NOTHROW_PROTO;
@@ -2225 +2242 @@
 #  endif */
     u64 = *pu64;
-# else /* !RT_ARCH_AMD64 */
+
+# elif defined(RT_ARCH_X86)
 #  if RT_INLINE_ASM_GNU_STYLE
 #   if defined(PIC) || defined(__PIC__)
@@ -2268 +2286 @@
     }
 #  endif
-# endif /* !RT_ARCH_AMD64 */
+
+# elif defined(RT_ARCH_ARM64)
+    Assert(!((uintptr_t)pu64 & 7));
+    u64 = *pu64;
+
+# elif defined(RT_ARCH_ARM32)
+    Assert(!((uintptr_t)pu64 & 7));
+    __asm__ __volatile__("ldrexd    %0, %H0, [%1]\n\t"
+                         : "=&r" (u64)
+                         : "r" (pu64)
+                         : );
+
+# else
+#  error "Port me"
+# endif
     return u64;
 }
@@ -2556 +2588 @@
 DECLINLINE(void) ASMAtomicWriteU8(volatile uint8_t RT_FAR *pu8, uint8_t u8) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgU8(pu8, u8);
 }
@@ -2580 +2613 @@
 DECLINLINE(void) ASMAtomicWriteS8(volatile int8_t RT_FAR *pi8, int8_t i8) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgS8(pi8, i8);
 }
@@ -2604 +2638 @@
 DECLINLINE(void) ASMAtomicWriteU16(volatile uint16_t RT_FAR *pu16, uint16_t u16) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgU16(pu16, u16);
 }
@@ -2629 +2664 @@
 DECLINLINE(void) ASMAtomicWriteS16(volatile int16_t RT_FAR *pi16, int16_t i16) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgS16(pi16, i16);
 }
@@ -2654 +2690 @@
 DECLINLINE(void) ASMAtomicWriteU32(volatile uint32_t RT_FAR *pu32, uint32_t u32) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgU32(pu32, u32);
 }
@@ -2712 +2749 @@
 DECLINLINE(void) ASMAtomicWriteU64(volatile uint64_t RT_FAR *pu64, uint64_t u64) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgU64(pu64, u64);
 }
@@ -2741 +2779 @@
 DECLINLINE(void) ASMAtomicWriteS64(volatile int64_t RT_FAR *pi64, int64_t i64) RT_NOTHROW_DEF
 {
+    /** @todo Any possible ARM32/ARM64 optimizations here? */
     ASMAtomicXchgS64(pi64, i64);
 }
@@ -3062 +3101 @@
  * @remarks x86: Requires a 486 or later.
  */
-#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
+#if RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN
 RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMAtomicAddU32(uint32_t volatile RT_FAR *pu32, uint32_t u32) RT_NOTHROW_PROTO;
 #else
@@ -3071 +3110 @@
     return u32;
 
-# elif RT_INLINE_ASM_GNU_STYLE
+# elif defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
+#  if RT_INLINE_ASM_GNU_STYLE
     __asm__ __volatile__("lock; xaddl %0, %1\n\t"
                          : "=r" (u32),
@@ -3079 +3119 @@
                          : "memory");
     return u32;
-# else
+#  else
     __asm
     {
         mov     eax, [u32]
-#  ifdef RT_ARCH_AMD64
+#   ifdef RT_ARCH_AMD64
         mov     rdx, [pu32]
         lock xadd [rdx], eax
-#  else
+#   else
         mov     edx, [pu32]
         lock xadd [edx], eax
-#  endif
+#   endif
         mov     [u32], eax
     }
     return u32;
+#  endif
+
+# elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
+    uint32_t u32Ret;
+    uint32_t rcSpill;
+    uint32_t u32Spill;
+    __asm__ __volatile__(".Ltry_again_add_u32_%=:\n\t"
+#  if defined(RT_ARCH_ARM64)
+                         "ldaxr     %w0, [%4]\n\t"
+                         "add       %w1, %w0, %w3\n\t"
+                         "stlxr     %w2, %w1, [%4]\n\t"
+                         "cbnz      %w2, .Ltry_again_add_u32_%=\n\t"
+#  else
+                         "ldrex     %0, [%4]\n\t"
+                         "add       %1, %0, %3\n\t"
+                         "strex     %2, %1, [%4]\n\t"
+                         "cmp       %2, #0\n\t"
+                         "bne       .Ltry_again_add_u32_%=\n\t"
+#  endif
+                         : "=&r" (u32Ret),
+                           "=&r" (u32Spill),
+                           "=&r" (rcSpill)
+                         : "r" (u32),
+                           "r" (pu32)
+                         : "memory",
+                           "cc");
+    return u32Ret;
+
+# else
+#  error "Port me"
 # endif
 }
@@ -3122 +3192 @@
  * @remarks x86: Requires a Pentium or later.
  */
-#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
+#if RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN
 DECLASM(uint64_t) ASMAtomicAddU64(uint64_t volatile RT_FAR *pu64, uint64_t u64) RT_NOTHROW_PROTO;
 #else
@@ -3139 +3209 @@
                          : "memory");
     return u64;
+
+# elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
+    uint64_t u64Ret;
+    uint32_t rcSpill;
+    uint64_t u64Spill;
+    __asm__ __volatile__(".Ltry_again_add_u64_%=:\n\t"
+#  if defined(RT_ARCH_ARM64)
+                         "ldaxr     %0, [%4]\n\t"
+                         "add       %1, %0, %3\n\t"
+                         "stlxr     %w2, %1, [%4]\n\t"
+                         "cbnz      %w2, .Ltry_again_add_u64_%=\n\t"
+#  else
+                         "ldrexd    %0, %H0, [%4]\n\t"
+                         "add       %1, %0, %3\n\t"
+                         "adc       %H1, %H0, %H3\n\t"
+                         "strexd    %2, %1, %H1, [%4]\n\t"
+                         "cmp       %2, #0\n\t"
+                         "bne       .Ltry_again_add_u64_%=\n\t"
+#  endif
+                         : "=&r" (u64Ret),
+                           "=&r" (u64Spill),
+                           "=&r" (rcSpill)
+                         : "r" (u64),
+                           "r" (pu64)
+                         : "memory",
+                           "cc");
+    return u64Ret;
+
 # else
     uint64_t u64Old;
@@ -3369 +3467 @@
  * @remarks x86: Requires a 486 or later.
  */
-#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
+#if RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN
 RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMAtomicIncU32(uint32_t volatile RT_FAR *pu32) RT_NOTHROW_PROTO;
 #else
 DECLINLINE(uint32_t) ASMAtomicIncU32(uint32_t volatile RT_FAR *pu32) RT_NOTHROW_DEF
 {
+# if RT_INLINE_ASM_USES_INTRIN
+    return (uint32_t)_InterlockedIncrement((long RT_FAR *)pu32);
+
+# elif defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
+#  if RT_INLINE_ASM_GNU_STYLE
     uint32_t u32;
-# if RT_INLINE_ASM_USES_INTRIN
-    u32 = _InterlockedIncrement((long RT_FAR *)pu32);
-    return u32;
-
-# elif RT_INLINE_ASM_GNU_STYLE
     __asm__ __volatile__("lock; xaddl %0, %1\n\t"
                          : "=r" (u32),
@@ -3387 +3485 @@
                          : "memory");
     return u32+1;
-# else
+#  else
     __asm
     {
         mov     eax, 1
-#  ifdef RT_ARCH_AMD64
+#   ifdef RT_ARCH_AMD64
         mov     rdx, [pu32]
         lock xadd [rdx], eax
-#  else
+#   else
         mov     edx, [pu32]
         lock xadd [edx], eax
-#  endif
+#   endif
         mov     u32, eax
     }
     return u32+1;
+#  endif
+
+# elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
+    uint32_t u32Ret;
+    uint32_t rcSpill;
+    __asm__ __volatile__(".Ltry_again_inc_u32_%=:\n\t"
+#  if defined(RT_ARCH_ARM64)
+                         "ldaxr     %w0, [%2]\n\t"
+                         "add       %w0, %w0, #1\n\t"
+                         "stlxr     %w1, %w0, [%2]\n\t"
+                         "cbnz      %w1, .Ltry_again_inc_u32_%=\n\t"
+#  else
+                         "ldrex     %0, [%2]\n\t"
+                         "add       %0, %0, #1\n\t" /* arm6 / thumb2+ */
+                         "strex     %1, %0, [%2]\n\t"
+                         "cmp       %1, #0\n\t"
+                         "bne       .Ltry_again_inc_u32_%=\n\t"
+#  endif
+                         : "=&r" (u32Ret),
+                           "=&r" (rcSpill)
+                         : "r" (pu32)
+                         : "memory",
+                           "cc");
+    return u32Ret;
+
+# else
+    return ASMAtomicAddU32(pu32, 1) + 1;
 # endif
 }
@@ -3428 +3553 @@
  * @remarks x86: Requires a Pentium or later.
  */
-#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
+#if RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN
 DECLASM(uint64_t) ASMAtomicIncU64(uint64_t volatile RT_FAR *pu64) RT_NOTHROW_PROTO;
 #else
@@ -3434 +3559 @@
 {
 # if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
-    uint64_t u64;
-    u64 = _InterlockedIncrement64((__int64 RT_FAR *)pu64);
-    return u64;
+    return (uint64_t)_InterlockedIncrement64((__int64 RT_FAR *)pu64);
 
 # elif RT_INLINE_ASM_GNU_STYLE && defined(RT_ARCH_AMD64)
@@ -3447 +3570 @@
                          : "memory");
     return u64 + 1;
+
+# elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
+    uint64_t u64Ret;
+    uint32_t rcSpill;
+    __asm__ __volatile__(".Ltry_again_inc_u64_%=:\n\t"
+#  if defined(RT_ARCH_ARM64)
+                         "ldaxr     %0, [%2]\n\t"
+                         "add       %0, %0, #1\n\t"
+                         "stlxr     %w1, %0, [%2]\n\t"
+                         "cbnz      %w1, .Ltry_again_inc_u64_%=\n\t"
+#  else
+                         "ldrexd    %0, %H0, [%2]\n\t"
+                         "add       %0, %0, #1\n\t" /* arm6 / thumb2+ */
+                         "adc       %H0, %H0, %3\n\t"
+                         "strexd    %1, %0, %H0, [%2]\n\t"
+                         "cmp       %1, #0\n\t"
+                         "bne       .Ltry_again_inc_u64_%=\n\t"
+#  endif
+                         : "=&r" (u64Ret),
+                           "=&r" (rcSpill)
+                         : "r" (pu64)
+#  if !defined(RT_ARCH_ARM64)
+                         , "r" (0)
+#  endif
+                         : "memory",
+                           "cc");
+    return u64Ret;
+
 # else
     return ASMAtomicAddU64(pu64, 1) + 1;
@@ -3511 +3662 @@
  * @remarks x86: Requires a 486 or later.
  */
-#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
+#if RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN
 RT_ASM_DECL_PRAGMA_WATCOM(uint32_t) ASMAtomicDecU32(uint32_t volatile RT_FAR *pu32) RT_NOTHROW_PROTO;
 #else
 DECLINLINE(uint32_t) ASMAtomicDecU32(uint32_t volatile RT_FAR *pu32) RT_NOTHROW_DEF
 {
+# if RT_INLINE_ASM_USES_INTRIN
+    return (uint32_t)_InterlockedDecrement((long RT_FAR *)pu32);
+
+# elif RT_INLINE_ASM_GNU_STYLE && defined(RT_ARCH_AMD64)
+#  if RT_INLINE_ASM_GNU_STYLE
     uint32_t u32;
-# if RT_INLINE_ASM_USES_INTRIN
-    u32 = _InterlockedDecrement((long RT_FAR *)pu32);
-    return u32;
-
-# elif RT_INLINE_ASM_GNU_STYLE
     __asm__ __volatile__("lock; xaddl %0, %1\n\t"
                          : "=r" (u32),
@@ -3530 +3681 @@
     return u32-1;
 # else
+    uint32_t u32;
     __asm
     {
@@ -3544 +3696 @@
     return u32-1;
 # endif
+
+# elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
+    uint32_t u32Ret;
+    uint32_t rcSpill;
+    __asm__ __volatile__(".Ltry_again_dec_u32_%=:\n\t"
+#  if defined(RT_ARCH_ARM64)
+                         "ldaxr     %w0, [%2]\n\t"
+                         "sub       %w0, %w0, #1\n\t"
+                         "stlxr     %w1, %w0, [%2]\n\t"
+                         "cbnz      %w1, .Ltry_again_dec_u32_%=\n\t"
+#  else
+                         "ldrex     %0, [%2]\n\t"
+                         "sub       %0, %0, #1\n\t" /* arm6 / thumb2+ */
+                         "strex     %1, %0, [%2]\n\t"
+                         "cmp       %1, #0\n\t"
+                         "bne       .Ltry_again_dec_u32_%=\n\t"
+#  endif
+                         : "=&r" (u32Ret),
+                           "=&r" (rcSpill)
+                         : "r" (pu32)
+                         : "memory",
+                           "cc");
+    return u32Ret;
+
+# else
+    return ASMAtomicSubU32(pu32, 1) - (uint32_t)1;
+# endif
 }
 #endif
@@ -3570 +3749 @@
  * @remarks x86: Requires a Pentium or later.
  */
-#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
+#if RT_INLINE_ASM_EXTERNAL_TMP_ARM && !RT_INLINE_ASM_USES_INTRIN
 RT_ASM_DECL_PRAGMA_WATCOM(uint64_t) ASMAtomicDecU64(uint64_t volatile RT_FAR *pu64) RT_NOTHROW_PROTO;
 #else
@@ -3576 +3755 @@
 {
 # if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
-    uint64_t u64 = _InterlockedDecrement64((__int64 volatile RT_FAR *)pu64);
-    return u64;
+    return (uint64_t)_InterlockedDecrement64((__int64 volatile RT_FAR *)pu64);
 
 # elif RT_INLINE_ASM_GNU_STYLE && defined(RT_ARCH_AMD64)
@@ -3588 +3766 @@
                          : "memory");
     return u64-1;
+
+# elif defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
+    uint64_t u64Ret;
+    uint32_t rcSpill;
+    __asm__ __volatile__(".Ltry_again_dec_u64_%=:\n\t"
+#  if defined(RT_ARCH_ARM64)
+                         "ldaxr     %0, [%2]\n\t"
+                         "sub       %0, %0, #1\n\t"
+                         "stlxr     %w1, %0, [%2]\n\t"
+                         "cbnz      %w1, .Ltry_again_dec_u64_%=\n\t"
+#  else
+                         "ldrexd    %0, %H0, [%2]\n\t"
+                         "sub       %0, %0, #1\n\t" /* arm6 / thumb2+ */
+                         "sbc       %H0, %H0, %3\n\t"
+                         "strexd    %1, %0, %H0, [%2]\n\t"
+                         "cmp       %1, #0\n\t"
+                         "bne       .Ltry_again_dec_u64_%=\n\t"
+#  endif
+                         : "=&r" (u64Ret),
+                           "=&r" (rcSpill)
+                         : "r" (pu64)
+#  if !defined(RT_ARCH_ARM64)
+                         , "r" (0)
+#  endif
+                         : "memory",
+                           "cc");
+    return u64Ret;
+
 # else
     return ASMAtomicAddU64(pu64, UINT64_MAX) - 1;