VirtualBox

Changeset 87479 in vbox


Ignore:
Timestamp:
Jan 29, 2021 2:46:18 PM (4 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
142501
Message:

VMM/HMVMX: Moving more stuff to HMR0PERVCPU. bugref:9217

Location:
trunk/src/VBox/VMM
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/HMAll.cpp

    r87472 r87479  
    493493 *                              StatTlbShootdownFlush or StatTlbShootdown.
    494494 */
    495 static void hmPokeCpuForTlbFlush(PVMCPU pVCpu, bool fAccountFlushStat)
     495static void hmPokeCpuForTlbFlush(PVMCPUCC pVCpu, bool fAccountFlushStat)
    496496{
    497497    if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
    … …  
    502502            STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
    503503#ifdef IN_RING0
    504         RTCPUID idHostCpu = pVCpu->hm.s.idEnteredCpu;
     504        RTCPUID idHostCpu = pVCpu->hmr0.s.idEnteredCpu;
    505505        if (idHostCpu != NIL_RTCPUID)
    506506            hmR0PokeCpu(pVCpu, idHostCpu);

  • trunk/src/VBox/VMM/VMMR0/HMR0.cpp

    r82968 r87479  
    11981198    {
    11991199        PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
    1200         pVCpu->hm.s.idEnteredCpu   = NIL_RTCPUID;
    1201         pVCpu->hm.s.idLastCpu      = NIL_RTCPUID;
     1200        pVCpu->hmr0.s.idEnteredCpu  = NIL_RTCPUID;
     1201        pVCpu->hmr0.s.idLastCpu     = NIL_RTCPUID;
    12021202
    12031203        /* We'll aways increment this the first time (host uses ASID 0). */
    1204         AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
     1204        AssertReturn(!pVCpu->hmr0.s.uCurrentAsid, VERR_HM_IPE_3);
    12051205    }
    12061206
    … …  
    13471347
    13481348    Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
    1349     pVCpu->hm.s.idEnteredCpu = idCpu;
     1349    pVCpu->hmr0.s.idEnteredCpu = idCpu;
    13501350    return rc;
    13511351}
    … …  
    13881388        /* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
    13891389        rc = g_HmR0.pfnEnterSession(pVCpu);
    1390         AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu),  pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
     1390        AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu),  pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
    13911391
    13921392        /* Exports the host-state as we may be resuming code after a longjmp and quite
    13931393           possibly now be scheduled on a different CPU. */
    13941394        rc = g_HmR0.pfnExportHostState(pVCpu);
    1395         AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu),  pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
     1395        AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu),  pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
    13961396
    13971397#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
    … …  
    14301430
    14311431        /* For obtaining a non-zero ASID/VPID on next re-entry. */
    1432         pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
     1432        pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
    14331433    }
    14341434
    14351435    /* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
    1436     pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
     1436    pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
    14371437
    14381438    /* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r87466 r87479  
    130130 *  used. */
    131131#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu)                  AssertMsg(   VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
    132                                                                   || (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
     132                                                                  || (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
    133133                                                                  ("Illegal migration! Entered on CPU %u Current %u\n", \
    134                                                                    (a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
     134                                                                   (a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()));
    135135
    136136/** Assert that we're not executing a nested-guest. */
    … …  
    12831283    bool fNewAsid = false;
    12841284    Assert(pHostCpu->idCpu != NIL_RTCPUID);
    1285     if (   pVCpu->hm.s.idLastCpu   != pHostCpu->idCpu
     1285    if (   pVCpu->hmr0.s.idLastCpu   != pHostCpu->idCpu
    12861286        || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
    12871287#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    … …  
    13131313    {
    13141314        pHostCpu->uCurrentAsid           = 1;
    1315         pVCpu->hm.s.uCurrentAsid         = 1;
     1315        pVCpu->hmr0.s.uCurrentAsid       = 1;
    13161316        pVCpu->hm.s.cTlbFlushes          = pHostCpu->cTlbFlushes;
    1317         pVCpu->hm.s.idLastCpu            = pHostCpu->idCpu;
     1317        pVCpu->hmr0.s.idLastCpu          = pHostCpu->idCpu;
    13181318        pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
    13191319
    … …  
    13481348                }
    13491349
    1350                 pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
    1351                 pVCpu->hm.s.idLastCpu    = pHostCpu->idCpu;
    1352                 pVCpu->hm.s.cTlbFlushes  = pHostCpu->cTlbFlushes;
     1350                pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
     1351                pVCpu->hmr0.s.idLastCpu    = pHostCpu->idCpu;
     1352                pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
    13531353            }
    13541354            else
    … …  
    13651365
    13661366    /* Update VMCB with the ASID. */
    1367     if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
    1368     {
    1369         pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
     1367    if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hmr0.s.uCurrentAsid)
     1368    {
     1369        pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hmr0.s.uCurrentAsid;
    13701370        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
    13711371    }
    13721372
    1373     AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
    1374               ("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
     1373    AssertMsg(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu,
     1374              ("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hmr0.s.idLastCpu, pHostCpu->idCpu));
    13751375    AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
    13761376              ("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
    13771377    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
    13781378              ("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
    1379     AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
    1380               ("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
     1379    AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
     1380              ("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
    13811381
    13821382#ifdef VBOX_WITH_STATISTICS
    … …  
    42224222    PHMPHYSCPU    pHostCpu         = hmR0GetCurrentCpu();
    42234223    RTCPUID const idHostCpu        = pHostCpu->idCpu;
    4224     bool const    fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
     4224    bool const    fMigratedHostCpu = idHostCpu != pVCpu->hmr0.s.idLastCpu;
    42254225
    42264226    /* Setup TSC offsetting. */
    … …  
    42654265    /* Flush the appropriate tagged-TLB entries. */
    42664266    hmR0SvmFlushTaggedTlb(pHostCpu,  pVCpu, pVmcb);
    4267     Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
     4267    Assert(pVCpu->hmr0.s.idLastCpu == idHostCpu);
    42684268
    42694269    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
    … …  
    45544554    {
    45554555        Assert(!HMR0SuspendPending());
    4556         AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
    4557                   ("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
     4556        AssertMsg(pVCpu->hmr0.s.idEnteredCpu == RTMpCpuId(),
     4557                  ("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hmr0.s.idEnteredCpu,
    45584558                  (unsigned)RTMpCpuId(), *pcLoops));
    45594559

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r87472 r87479  
    162162 *  used. */
    163163#define HMVMX_ASSERT_CPU_SAFE(a_pVCpu)              AssertMsg(   VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
    164                                                               || (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
     164                                                              || (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
    165165                                                              ("Illegal migration! Entered on CPU %u Current %u\n", \
    166                                                               (a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()))
     166                                                              (a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()))
    167167
    168168/** Asserts that the given CPUMCTX_EXTRN_XXX bits are present in the guest-CPU
    … …  
    29102910    {
    29112911        AssertPtr(pVCpu);
    2912         AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
    2913         AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
    2914         au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
     2912        AssertMsg(pVCpu->hmr0.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hmr0.s.uCurrentAsid));
     2913        AssertMsg(pVCpu->hmr0.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hmr0.s.uCurrentAsid));
     2914        au64Descriptor[0] = pVCpu->hmr0.s.uCurrentAsid;
    29152915        au64Descriptor[1] = GCPtr;
    29162916    }
    … …  
    29182918    int rc = VMXR0InvVPID(enmTlbFlush, &au64Descriptor[0]);
    29192919    AssertMsg(rc == VINF_SUCCESS,
    2920               ("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
     2920              ("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hmr0.s.uCurrentAsid : 0, GCPtr, rc));
    29212921
    29222922    if (   RT_SUCCESS(rc)
    … …  
    29862986
    29872987    Assert(pHostCpu->idCpu != NIL_RTCPUID);
    2988     pVCpu->hm.s.idLastCpu      = pHostCpu->idCpu;
     2988    pVCpu->hmr0.s.idLastCpu    = pHostCpu->idCpu;
    29892989    pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
    29902990    pVCpu->hm.s.fForceTLBFlush = false;
    … …  
    30353035     * cannot reuse the current ASID anymore.
    30363036     */
    3037     if (   pVCpu->hm.s.idLastCpu  != pHostCpu->idCpu
     3037    if (   pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
    30383038        || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
    30393039    {
    … …  
    30463046        }
    30473047
    3048         pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
    3049         pVCpu->hm.s.idLastCpu    = pHostCpu->idCpu;
    3050         pVCpu->hm.s.cTlbFlushes  = pHostCpu->cTlbFlushes;
     3048        pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
     3049        pVCpu->hmr0.s.idLastCpu    = pHostCpu->idCpu;
     3050        pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
    30513051
    30523052        /*
    … …  
    30923092    HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
    30933093
    3094     Assert(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu);
     3094    Assert(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu);
    30953095    Assert(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes);
    30963096    AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
    … …  
    30983098    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
    30993099              ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
    3100                pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
    3101     AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
    3102               ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
     3100               pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
     3101    AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
     3102              ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
    31033103
    31043104    /* Update VMCS with the VPID. */
    3105     int rc  = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
     3105    int rc  = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid);
    31063106    AssertRC(rc);
    31073107
    … …  
    31313131     * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
    31323132     */
    3133     if (   pVCpu->hm.s.idLastCpu   != pHostCpu->idCpu
     3133    if (   pVCpu->hmr0.s.idLastCpu   != pHostCpu->idCpu
    31343134        || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
    31353135    {
    … …  
    31533153    }
    31543154
    3155     pVCpu->hm.s.idLastCpu  = pHostCpu->idCpu;
     3155    pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
    31563156    pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
    31573157
    … …  
    31863186     * cannot reuse the current ASID anymore.
    31873187     */
    3188     if (   pVCpu->hm.s.idLastCpu  != pHostCpu->idCpu
     3188    if (   pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
    31893189        || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
    31903190    {
    … …  
    32153215
    32163216    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    3217     pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
     3217    pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
    32183218    if (pVCpu->hm.s.fForceTLBFlush)
    32193219    {
    … …  
    32283228        pVCpu->hm.s.fForceTLBFlush = false;
    32293229        pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
    3230         pVCpu->hm.s.uCurrentAsid   = pHostCpu->uCurrentAsid;
     3230        pVCpu->hmr0.s.uCurrentAsid   = pHostCpu->uCurrentAsid;
    32313231        if (pHostCpu->fFlushAsidBeforeUse)
    32323232        {
    … …  
    32503250    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
    32513251              ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
    3252                pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
    3253     AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
    3254               ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
    3255 
    3256     int rc  = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
     3252               pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
     3253    AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
     3254              ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
     3255
     3256    int rc  = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid);
    32573257    AssertRC(rc);
    32583258}
    … …  
    69156915            hmR0VmxReadExitQualVmcs(pVmxTransient);
    69166916
    6917             pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
     6917            pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hmr0.s.idEnteredCpu;
    69186918            /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
    69196919               Cannot do it here as we may have been long preempted. */
    … …  
    84948494        VMXGetCurrentVmcs(&pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs);
    84958495        pVCpu->hm.s.vmx.LastError.u32VmcsRev   = *(uint32_t *)pVmcsInfo->pvVmcs;
    8496         pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
     8496        pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hmr0.s.idEnteredCpu;
    84978497        /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
    84988498    }
    … …  
    1101911019     */
    1102011020    if (   !pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer
    11021         || idCurrentCpu != pVCpu->hm.s.idLastCpu)
     11021        || idCurrentCpu != pVCpu->hmr0.s.idLastCpu)
    1102211022    {
    1102311023        hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu, pVmxTransient);
    … …  
    1103411034    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);    /* Used for TLB flushing, set this across the world switch. */
    1103511035    hmR0VmxFlushTaggedTlb(pHostCpu, pVCpu, pVmcsInfo);          /* Invalidate the appropriate guest entries from the TLB. */
    11036     Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
     11036    Assert(idCurrentCpu == pVCpu->hmr0.s.idLastCpu);
    1103711037    pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu;      /* Record the error reporting info. with the current host CPU. */
    1103811038    pVmcsInfo->idHostCpuState = idCurrentCpu;                   /* Record the CPU for which the host-state has been exported. */
    … …  
    1435414354
    1435514355#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
    14356     PCVMXVMCSINFO       pVmcsInfo       = pVmxTransient->pVmcsInfo;
    14357     PCVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared;
    14358     AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVmcsInfoShared->RealMode.fRealOnV86Active || pVmxTransient->fIsNestedGuest,
     14356    PCVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
     14357    AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVmcsInfo->pShared->RealMode.fRealOnV86Active || pVmxTransient->fIsNestedGuest,
    1435914358              ("uVector=%#x u32XcptBitmap=%#X32\n",
    1436014359               VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo), pVmcsInfo->u32XcptBitmap));

  • trunk/src/VBox/VMM/include/HMInternal.h

    r87472 r87479  
    10011001    /** World switch exit counter. */
    10021002    uint32_t volatile           cWorldSwitchExits;
    1003     /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
    1004     RTCPUID                     idLastCpu;
    10051003    /** TLB flush count. */
    10061004    uint32_t                    cTlbFlushes;
    1007     /** Current ASID in use by the VM. */
    1008     uint32_t                    uCurrentAsid;
    10091005    /** An additional error code used for some gurus. */
    10101006    uint32_t                    u32HMError;
    … …  
    11041100    HMEVENT                 Event;
    11051101
    1106     /** The CPU ID of the CPU currently owning the VMCS. Set in
    1107      * HMR0Enter and cleared in HMR0Leave. */
    1108     RTCPUID                 idEnteredCpu;
    1109 
    11101102    /** Current shadow paging mode for updating CR4. */
    11111103    PGMMODE                 enmShadowMode;
     1104    uint32_t                u32TemporaryPadding;
    11121105
    11131106    /** The PAE PDPEs used with Nested Paging (only valid when
    … …  
    12831276typedef struct HMR0PERVCPU
    12841277{
     1278    /** Current ASID in use by the VM. */
     1279    uint32_t                    uCurrentAsid;
     1280    /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
     1281    RTCPUID                     idLastCpu;
     1282    /** The CPU ID of the CPU currently owning the VMCS. Set in
     1283     * HMR0Enter and cleared in HMR0Leave. */
     1284    RTCPUID                     idEnteredCpu;
     1285
     1286    uint32_t                    u32Padding0;
     1287
    12851288    union HM_NAMELESS_UNION_TAG(HMR0CPUUNION) /* no tag! */
    12861289    {

  • trunk/src/VBox/VMM/include/HMInternal.mac

    r87472 r87479  
    176176
    177177    .cWorldSwitchExits              resd    1
    178     .idLastCpu                      resd    1
    179178    .cTlbFlushes                    resd    1
    180     .uCurrentAsid                   resd    1
    181179    .u32HMError                     resd    1
    182180    .rcLastExitToR3                 resd    1
    … …  
    198196    .Event.GCPtrFaultAddress        RTGCPTR_RES 1
    199197
    200     .idEnteredCpu                   resd    1
    201198    .enmShadowMode                  resd    1
    202199    alignb 8
    … …  
    231228
    232229struc HMR0PERVCPU
     230    .uCurrentAsid                   resd    1
     231    .idLastCpu                      resd    1
     232    .idEnteredCpu                   resd    1
     233
    233234    alignb 8
    234235;%if HMR0CPUVMX_size > HMR0CPUSVM_size
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