Index: /trunk/src/VBox/VMM/VMMR0/HMR0A.asm
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMR0A.asm	(revision 87502)
+++ /trunk/src/VBox/VMM/VMMR0/HMR0A.asm	(revision 87503)
@@ -1350,5 +1350,5 @@
 
         ; Save host fs, gs, sysenter msr etc.
-        mov     rax, [rsi + VMCPU.hm + HMCPU.svm + HMCPUSVM.HCPhysVmcbHost]
+        mov     rax, [rsi + GVMCPU.hmr0 + HMR0PERVCPU.svm + HMR0CPUSVM.HCPhysVmcbHost]
         mov     qword [rbp + frm_HCPhysVmcbHost], rax ; save for the vmload after vmrun
         lea     rsi, [rsi + VMCPU.cpum.GstCtx]
Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 87502)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 87503)
@@ -678,25 +678,25 @@
         AssertPtr(pVCpu);
 
-        if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
-        {
-            RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
-            pVCpu->hm.s.svm.HCPhysVmcbHost   = 0;
-            pVCpu->hm.s.svm.hMemObjVmcbHost  = NIL_RTR0MEMOBJ;
-        }
-
-        if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
-        {
-            RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
-            pVCpu->hm.s.svm.pVmcb            = NULL;
-            pVCpu->hm.s.svm.HCPhysVmcb       = 0;
-            pVCpu->hm.s.svm.hMemObjVmcb      = NIL_RTR0MEMOBJ;
-        }
-
-        if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
-        {
-            RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
-            pVCpu->hm.s.svm.pvMsrBitmap      = NULL;
-            pVCpu->hm.s.svm.HCPhysMsrBitmap  = 0;
-            pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
+        if (pVCpu->hmr0.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
+        {
+            RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcbHost, false);
+            pVCpu->hmr0.s.svm.HCPhysVmcbHost   = 0;
+            pVCpu->hmr0.s.svm.hMemObjVmcbHost  = NIL_RTR0MEMOBJ;
+        }
+
+        if (pVCpu->hmr0.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
+        {
+            RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcb, false);
+            pVCpu->hmr0.s.svm.pVmcb            = NULL;
+            pVCpu->hmr0.s.svm.HCPhysVmcb       = 0;
+            pVCpu->hmr0.s.svm.hMemObjVmcb      = NIL_RTR0MEMOBJ;
+        }
+
+        if (pVCpu->hmr0.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
+        {
+            RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, false);
+            pVCpu->hmr0.s.svm.pvMsrBitmap      = NULL;
+            pVCpu->hmr0.s.svm.HCPhysMsrBitmap  = 0;
+            pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
         }
     }
@@ -778,7 +778,7 @@
     {
         PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
-        pVCpu->hm.s.svm.hMemObjVmcbHost  = NIL_RTR0MEMOBJ;
-        pVCpu->hm.s.svm.hMemObjVmcb      = NIL_RTR0MEMOBJ;
-        pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
+        pVCpu->hmr0.s.svm.hMemObjVmcbHost  = NIL_RTR0MEMOBJ;
+        pVCpu->hmr0.s.svm.hMemObjVmcb      = NIL_RTR0MEMOBJ;
+        pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
     }
 
@@ -797,11 +797,12 @@
          * FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
          */
-        rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
+/** @todo Does this need to be below 4G? */
+        rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
         if (RT_FAILURE(rc))
             goto failure_cleanup;
 
-        void *pvVmcbHost               = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
-        pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
-        Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
+        void *pvVmcbHost                    = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcbHost);
+        pVCpu->hmr0.s.svm.HCPhysVmcbHost    = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcbHost, 0 /* iPage */);
+        Assert(pVCpu->hmr0.s.svm.HCPhysVmcbHost < _4G);
         ASMMemZeroPage(pvVmcbHost);
 
@@ -809,12 +810,13 @@
          * Allocate one page for the guest-state VMCB.
          */
-        rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
+/** @todo Does this need to be below 4G? */
+        rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
         if (RT_FAILURE(rc))
             goto failure_cleanup;
 
-        pVCpu->hm.s.svm.pVmcb           = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
-        pVCpu->hm.s.svm.HCPhysVmcb      = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
-        Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
-        ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
+        pVCpu->hmr0.s.svm.pVmcb             = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcb);
+        pVCpu->hmr0.s.svm.HCPhysVmcb        = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcb, 0 /* iPage */);
+        Assert(pVCpu->hmr0.s.svm.HCPhysVmcb < _4G);
+        ASMMemZeroPage(pVCpu->hmr0.s.svm.pVmcb);
 
         /*
@@ -822,13 +824,14 @@
          * SVM to not require one.
          */
-        rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
+/** @todo Does this need to be below 4G? */
+        rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
                                  false /* fExecutable */);
         if (RT_FAILURE(rc))
             goto failure_cleanup;
 
-        pVCpu->hm.s.svm.pvMsrBitmap     = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
-        pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
+        pVCpu->hmr0.s.svm.pvMsrBitmap       = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjMsrBitmap);
+        pVCpu->hmr0.s.svm.HCPhysMsrBitmap   = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
         /* Set all bits to intercept all MSR accesses (changed later on). */
-        ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
+        ASMMemFill32(pVCpu->hmr0.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
    }
 
@@ -1007,5 +1010,5 @@
 
     PVMCPUCC     pVCpu0 = VMCC_GET_CPU_0(pVM);
-    PSVMVMCB     pVmcb0 = pVCpu0->hm.s.svm.pVmcb;
+    PSVMVMCB     pVmcb0 = pVCpu0->hmr0.s.svm.pVmcb;
     AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
     PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
@@ -1142,5 +1145,5 @@
      * Don't intercept guest read/write accesses to these MSRs.
      */
-    uint8_t *pbMsrBitmap0 = (uint8_t *)pVCpu0->hm.s.svm.pvMsrBitmap;
+    uint8_t *pbMsrBitmap0 = (uint8_t *)pVCpu0->hmr0.s.svm.pvMsrBitmap;
     hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR,          SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
     hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR,          SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
@@ -1162,5 +1165,5 @@
         hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
     }
-    pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hm.s.svm.HCPhysMsrBitmap;
+    pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hmr0.s.svm.HCPhysMsrBitmap;
 
     /* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
@@ -1170,5 +1173,5 @@
     {
         PVMCPUCC     pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
-        PSVMVMCB     pVmcbCur = pVCpuCur->hm.s.svm.pVmcb;
+        PSVMVMCB     pVmcbCur = pVCpuCur->hmr0.s.svm.pVmcb;
         AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
         PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
@@ -1178,7 +1181,7 @@
 
         /* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
-        uint8_t *pbMsrBitmapCur = (uint8_t *)pVCpuCur->hm.s.svm.pvMsrBitmap;
+        uint8_t *pbMsrBitmapCur = (uint8_t *)pVCpuCur->hmr0.s.svm.pvMsrBitmap;
         memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
-        pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
+        pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hmr0.s.svm.HCPhysMsrBitmap;
 
         /* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
@@ -1211,5 +1214,5 @@
         return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
 #endif
-    return pVCpu->hm.s.svm.pVmcb;
+    return pVCpu->hmr0.s.svm.pVmcb;
 }
 
@@ -2127,5 +2130,5 @@
                 /* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
                 pVmcb->guest.u64LSTAR = u8Tpr;
-                uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
+                uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hmr0.s.svm.pvMsrBitmap;
 
                 /* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
@@ -2193,6 +2196,6 @@
 static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
 {
-    PVMCC          pVM             = pVCpu->CTX_SUFF(pVM);
-    PCSVMVMCB    pVmcb           = pVCpu->hm.s.svm.pVmcb;
+    PVMCC        pVM             = pVCpu->CTX_SUFF(pVM);
+    PCSVMVMCB    pVmcb           = pVCpu->hmr0.s.svm.pVmcb;
     PSVMVMCB     pVmcbNstGst     = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
     PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
@@ -2470,5 +2473,5 @@
 DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
 {
-    uint64_t const *pu64GstMsrpm    = (uint64_t const *)pVCpu->hm.s.svm.pvMsrBitmap;
+    uint64_t const *pu64GstMsrpm    = (uint64_t const *)pVCpu->hmr0.s.svm.pvMsrBitmap;
     uint64_t const *pu64NstGstMsrpm = (uint64_t const *)pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
     uint64_t       *pu64DstMsrpm    = (uint64_t *)pHostCpu->n.svm.pvNstGstMsrpm;
@@ -2956,5 +2959,5 @@
     if (CPUMIsHyperDebugStateActive(pVCpu))
     {
-        PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
+        PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb; /** @todo nested-guest. */
         Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
         Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
@@ -4129,5 +4132,5 @@
     {
         Assert(!pSvmTransient->fIsNestedGuest);
-        PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
+        PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
         if (pVM->hm.s.fTPRPatchingActive)
             pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
@@ -4249,5 +4252,5 @@
     uint8_t *pbMsrBitmap;
     if (!pSvmTransient->fIsNestedGuest)
-        pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
+        pbMsrBitmap = (uint8_t *)pVCpu->hmr0.s.svm.pvMsrBitmap;
     else
     {
@@ -4469,5 +4472,5 @@
     RT_ZERO(SvmTransient);
     SvmTransient.fUpdateTscOffsetting = true;
-    SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
+    SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
 
     VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
@@ -4491,5 +4494,5 @@
          */
         hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
-        rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
+        rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
 
         /* Restore any residual host-state and save any bits shared between host and guest
@@ -4510,5 +4513,5 @@
         HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
         STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
-        VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
+        VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
         rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
         STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
@@ -4544,5 +4547,5 @@
     RT_ZERO(SvmTransient);
     SvmTransient.fUpdateTscOffsetting = true;
-    SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
+    SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
 
     PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
@@ -4573,5 +4576,5 @@
         hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
 
-        rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
+        rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
 
         /* Restore any residual host-state and save any bits shared between host and guest
@@ -4592,5 +4595,5 @@
         HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
         STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
-        VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
+        VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
         rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
         STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
@@ -6484,5 +6487,5 @@
 
             /* Don't intercept DRx read and writes. */
-            PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
+            PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
             pVmcb->ctrl.u16InterceptRdDRx = 0;
             pVmcb->ctrl.u16InterceptWrDRx = 0;
@@ -7296,5 +7299,5 @@
 
     /* Paranoia; Ensure we cannot be called as a result of event delivery. */
-    PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
+    PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
     Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);  NOREF(pVmcb);
 
@@ -7453,5 +7456,5 @@
      */
     PVMCC      pVM   = pVCpu->CTX_SUFF(pVM);
-    PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
+    PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
     PCPUMCTX pCtx  = &pVCpu->cpum.GstCtx;
     int rc = DBGFTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
Index: /trunk/src/VBox/VMM/include/HMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/HMInternal.h	(revision 87502)
+++ /trunk/src/VBox/VMM/include/HMInternal.h	(revision 87503)
@@ -1018,26 +1018,4 @@
     struct HMCPUSVM
     {
-        /** Physical address of the host VMCB which holds additional host-state. */
-        RTHCPHYS                    HCPhysVmcbHost;
-        /** R0 memory object for the host VMCB which holds additional host-state. */
-        RTR0MEMOBJ                  hMemObjVmcbHost;
-        /** Padding.
-         * @todo remove, pointless now  */
-        R0PTRTYPE(void *)           pvPadding;
-
-        /** Physical address of the guest VMCB. */
-        RTHCPHYS                    HCPhysVmcb;
-        /** R0 memory object for the guest VMCB. */
-        RTR0MEMOBJ                  hMemObjVmcb;
-        /** Pointer to the guest VMCB. */
-        R0PTRTYPE(PSVMVMCB)         pVmcb;
-
-        /** Physical address of the MSR bitmap (8 KB). */
-        RTHCPHYS                    HCPhysMsrBitmap;
-        /** R0 memory object for the MSR bitmap (8 KB). */
-        RTR0MEMOBJ                  hMemObjMsrBitmap;
-        /** Pointer to the MSR bitmap. */
-        R0PTRTYPE(void *)           pvMsrBitmap;
-
         /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
          *  we should check if the VTPR changed on every VM-exit. */
@@ -1320,4 +1298,23 @@
         PFNHMSVMVMRUN               pfnVMRun;
 
+        /** Physical address of the host VMCB which holds additional host-state. */
+        RTHCPHYS                    HCPhysVmcbHost;
+        /** R0 memory object for the host VMCB which holds additional host-state. */
+        RTR0MEMOBJ                  hMemObjVmcbHost;
+
+        /** Physical address of the guest VMCB. */
+        RTHCPHYS                    HCPhysVmcb;
+        /** R0 memory object for the guest VMCB. */
+        RTR0MEMOBJ                  hMemObjVmcb;
+        /** Pointer to the guest VMCB. */
+        R0PTRTYPE(PSVMVMCB)         pVmcb;
+
+        /** Physical address of the MSR bitmap (8 KB). */
+        RTHCPHYS                    HCPhysMsrBitmap;
+        /** R0 memory object for the MSR bitmap (8 KB). */
+        RTR0MEMOBJ                  hMemObjMsrBitmap;
+        /** Pointer to the MSR bitmap. */
+        R0PTRTYPE(void *)           pvMsrBitmap;
+
         /** For saving stack space, the disassembler state is allocated here
          * instead of on the stack. */
Index: /trunk/src/VBox/VMM/include/HMInternal.mac
===================================================================
--- /trunk/src/VBox/VMM/include/HMInternal.mac	(revision 87502)
+++ /trunk/src/VBox/VMM/include/HMInternal.mac	(revision 87503)
@@ -137,17 +137,4 @@
 
 struc HMCPUSVM
-    .HCPhysVmcbHost                 RTHCPHYS_RES 1
-
-    .hMemObjVmcbHost                RTR0PTR_RES  1
-    .pvPadding                      RTR0PTR_RES  1 ; pointless padding
-
-    .HCPhysVmcb                     RTHCPHYS_RES 1
-    .hMemObjVmcb                    RTR0PTR_RES  1
-    .pVmcb                          RTR0PTR_RES  1
-
-    .HCPhysMsrBitmap                RTHCPHYS_RES 1
-    .hMemObjMsrBitmap               RTR0PTR_RES  1
-    .pvMsrBitmap                    RTR0PTR_RES  1
-
     .fSyncVTpr                      resb    1
     .fEmulateLongModeSysEnterExit   resb    1
@@ -219,4 +206,20 @@
     .pfnVMRun                       RTR0PTR_RES  1
 
+    alignb 8
+    .HCPhysVmcbHost                 RTHCPHYS_RES 1
+
+    alignb 8
+    .hMemObjVmcbHost                RTR0PTR_RES  1
+
+    alignb 8
+    .HCPhysVmcb                     RTHCPHYS_RES 1
+    .hMemObjVmcb                    RTR0PTR_RES  1
+    .pVmcb                          RTR0PTR_RES  1
+
+    alignb 8
+    .HCPhysMsrBitmap                RTHCPHYS_RES 1
+    .hMemObjMsrBitmap               RTR0PTR_RES  1
+    .pvMsrBitmap                    RTR0PTR_RES  1
+
     .DisState                       resb    0d8h
 endstruc
