Changeset 87504 in vbox

Timestamp:

Feb 1, 2021 3:12:21 PM (4 years ago)

Author:

vboxsync

Message:

VMM/HMSVM: Moving more stuff to HMR0PERVCPU. bugref:9217

Location:

trunk

Files:

• include/VBox/vmm/hm_svm.h (modified) (2 diffs)
• src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (9 diffs)
• src/VBox/VMM/include/HMInternal.h (modified) (3 diffs)
• src/VBox/VMM/include/HMInternal.mac (modified) (2 diffs)

trunk/include/VBox/vmm/hm_svm.h

@@ -1079 +1079 @@
  * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
  *          this structure.
- */
-#pragma pack(1)
+ * @todo r=bird: Why is this structure here? Looks 100% internal to me.
+ */
 typedef struct SVMNESTEDVMCBCACHE
 {
@@ -1116 +1116 @@
     bool                afPadding0[4];
 } SVMNESTEDVMCBCACHE;
-#pragma pack()
 /** Pointer to the SVMNESTEDVMCBCACHE structure. */
 typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -2107 +2107 @@
                every #VMEXIT if we should update the TPR. */
             Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
-            pVCpu->hm.s.svm.fSyncVTpr = false;
+            pVCpu->hmr0.s.svm.fSyncVTpr = false;
 
             if (!pVM->hm.s.fTPRPatchingActive)
@@ -2121 +2121 @@
                 {
                     pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
-                    pVCpu->hm.s.svm.fSyncVTpr = true;
+                    pVCpu->hmr0.s.svm.fSyncVTpr = true;
                 }
 
@@ -2138 +2138 @@
                 {
                     hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
-                    pVCpu->hm.s.svm.fSyncVTpr = true;
+                    pVCpu->hmr0.s.svm.fSyncVTpr = true;
                 }
                 pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
@@ -2571 +2571 @@
          * to the nested-guest intercepts and we always run with V_INTR_MASKING.
          */
-        pVCpu->hm.s.svm.fSyncVTpr = false;
+        pVCpu->hmr0.s.svm.fSyncVTpr = false;
 
 #ifdef DEBUG_ramshankar
@@ -2602 +2602 @@
     else
     {
-        Assert(!pVCpu->hm.s.svm.fSyncVTpr);
+        Assert(!pVCpu->hmr0.s.svm.fSyncVTpr);
         Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
         Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
@@ -4129 +4129 @@
      * world-switch so we can update it on the way back if the guest changed the TPR.
      */
-    if (pVCpu->hm.s.svm.fSyncVTpr)
+    if (pVCpu->hmr0.s.svm.fSyncVTpr)
     {
         Assert(!pSvmTransient->fIsNestedGuest);
@@ -4285 +4285 @@
     {
         uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
-        pVCpu->hm.s.svm.u64HostTscAux   = ASMRdMsr(MSR_K8_TSC_AUX);
-        if (uGuestTscAux != pVCpu->hm.s.svm.u64HostTscAux)
+        pVCpu->hmr0.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
+        if (uGuestTscAux != pVCpu->hmr0.s.svm.u64HostTscAux)
             ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
         hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
@@ -4368 +4368 @@
         uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
         CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
-        if (u64GuestTscAuxMsr != pVCpu->hm.s.svm.u64HostTscAux)
-            ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.svm.u64HostTscAux);
+        if (u64GuestTscAuxMsr != pVCpu->hmr0.s.svm.u64HostTscAux)
+            ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hmr0.s.svm.u64HostTscAux);
     }
 
@@ -4421 +4421 @@
 
     if (   pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
-        && pVCpu->hm.s.svm.fSyncVTpr)
+        && pVCpu->hmr0.s.svm.fSyncVTpr)
     {
         Assert(!pSvmTransient->fIsNestedGuest);

trunk/src/VBox/VMM/include/HMInternal.h

@@ -1018 +1018 @@
     struct HMCPUSVM
     {
-        /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
-         *  we should check if the VTPR changed on every VM-exit. */
-        bool                        fSyncVTpr;
         /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
          *  does.   This means intercepting \#UD to emulate the instructions in
@@ -1026 +1023 @@
          *  preserve the upper 32 bits written to them (AMD will ignore and discard). */
         bool                        fEmulateLongModeSysEnterExit;
-        uint8_t                     au8Alignment0[6];
-
-        /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
-        uint64_t                    u64HostTscAux;
+        uint8_t                     au8Alignment0[7];
 
         /** Cache of the nested-guest's VMCB fields that we modify in order to run the
@@ -1317 +1311 @@
         R0PTRTYPE(void *)           pvMsrBitmap;
 
+        /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
+         *  we should check if the VTPR changed on every VM-exit. */
+        bool                        fSyncVTpr;
+        bool                        afAlignment[7];
+
+        /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
+        uint64_t                    u64HostTscAux;
+
         /** For saving stack space, the disassembler state is allocated here
          * instead of on the stack. */

trunk/src/VBox/VMM/include/HMInternal.mac

@@ -137 +137 @@
 
 struc HMCPUSVM
-    .fSyncVTpr                      resb    1
     .fEmulateLongModeSysEnterExit   resb    1
 
     alignb 8
-    .u64HostTscAux                  resq    1
-
     .NstGstVmcbCache                resb    40
 endstruc
@@ -222 +219 @@
     .pvMsrBitmap                    RTR0PTR_RES  1
 
+    .fSyncVTpr                      resb    1
+
+    alignb 8
+    .u64HostTscAux                  resq    1
+
+    alignb 8
     .DisState                       resb    0d8h
 endstruc