- Timestamp:
- Feb 2, 2021 11:39:13 AM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 142557
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
-
VMMR0/HMVMXR0.cpp (modified) (18 diffs)
-
VMMR3/HM.cpp (modified) (1 diff)
-
include/HMInternal.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r87530 r87531 1980 1980 if (pVM->hm.s.vmx.fUseVmcsShadowing) 1981 1981 { 1982 RTMemFree(pVM->hm .s.vmx.paShadowVmcsFields);1983 pVM->hm .s.vmx.paShadowVmcsFields = NULL;1984 RTMemFree(pVM->hm .s.vmx.paShadowVmcsRoFields);1985 pVM->hm .s.vmx.paShadowVmcsRoFields = NULL;1982 RTMemFree(pVM->hmr0.s.vmx.paShadowVmcsFields); 1983 pVM->hmr0.s.vmx.paShadowVmcsFields = NULL; 1984 RTMemFree(pVM->hmr0.s.vmx.paShadowVmcsRoFields); 1985 pVM->hmr0.s.vmx.paShadowVmcsRoFields = NULL; 1986 1986 } 1987 1987 #endif … … 2031 2031 VMXPAGEALLOCINFO aAllocInfo[] = 2032 2032 { 2033 { fVirtApicAccess, 0 /* Unused */, &pVM->hm .s.vmx.HCPhysApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess },2034 { fUseVmcsShadowing, 0 /* Unused */, &pVM->hm .s.vmx.HCPhysVmreadBitmap, &pVM->hm.s.vmx.pvVmreadBitmap },2035 { fUseVmcsShadowing, 0 /* Unused */, &pVM->hm .s.vmx.HCPhysVmwriteBitmap, &pVM->hm.s.vmx.pvVmwriteBitmap },2033 { fVirtApicAccess, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysApicAccess, (PRTR0PTR)&pVM->hmr0.s.vmx.pbApicAccess }, 2034 { fUseVmcsShadowing, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysVmreadBitmap, &pVM->hmr0.s.vmx.pvVmreadBitmap }, 2035 { fUseVmcsShadowing, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysVmwriteBitmap, &pVM->hmr0.s.vmx.pvVmwriteBitmap }, 2036 2036 #ifdef VBOX_WITH_CRASHDUMP_MAGIC 2037 { true, 0 /* Unused */, &pVM->hm .s.vmx.HCPhysScratch, &(PRTR0PTR)pVM->hm.s.vmx.pbScratch },2037 { true, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysScratch, (PRTR0PTR)&pVM->hmr0.s.vmx.pbScratch }, 2038 2038 #endif 2039 2039 }; … … 2046 2046 if (fUseVmcsShadowing) 2047 2047 { 2048 Assert(!pVM->hm .s.vmx.cShadowVmcsFields);2049 Assert(!pVM->hm .s.vmx.cShadowVmcsRoFields);2050 pVM->hm .s.vmx.paShadowVmcsFields = (uint32_t *)RTMemAllocZ(sizeof(g_aVmcsFields));2051 pVM->hm .s.vmx.paShadowVmcsRoFields = (uint32_t *)RTMemAllocZ(sizeof(g_aVmcsFields));2052 if (!pVM->hm .s.vmx.paShadowVmcsFields || !pVM->hm.s.vmx.paShadowVmcsRoFields)2048 Assert(!pVM->hmr0.s.vmx.cShadowVmcsFields); 2049 Assert(!pVM->hmr0.s.vmx.cShadowVmcsRoFields); 2050 pVM->hmr0.s.vmx.paShadowVmcsFields = (uint32_t *)RTMemAllocZ(sizeof(g_aVmcsFields)); 2051 pVM->hmr0.s.vmx.paShadowVmcsRoFields = (uint32_t *)RTMemAllocZ(sizeof(g_aVmcsFields)); 2052 if (!pVM->hmr0.s.vmx.paShadowVmcsFields || !pVM->hmr0.s.vmx.paShadowVmcsRoFields) 2053 2053 rc = VERR_NO_MEMORY; 2054 2054 } … … 2086 2086 { 2087 2087 /* Paranoia. */ 2088 Assert(pVM->hm .s.vmx.pbApicAccess == NULL);2088 Assert(pVM->hmr0.s.vmx.pbApicAccess == NULL); 2089 2089 #ifdef VBOX_WITH_CRASHDUMP_MAGIC 2090 Assert(pVM->hm .s.vmx.pbScratch == NULL);2090 Assert(pVM->hmr0.s.vmx.pbScratch == NULL); 2091 2091 #endif 2092 2092 … … 2095 2095 */ 2096 2096 #ifdef VBOX_WITH_CRASHDUMP_MAGIC 2097 pVM->hm .s.vmx.HCPhysScratch= NIL_RTHCPHYS;2097 pVM->hmr0.s.vmx.HCPhysScratch = NIL_RTHCPHYS; 2098 2098 #endif 2099 pVM->hm .s.vmx.HCPhysApicAccess = NIL_RTHCPHYS;2100 pVM->hm .s.vmx.HCPhysVmreadBitmap = NIL_RTHCPHYS;2101 pVM->hm .s.vmx.HCPhysVmwriteBitmap = NIL_RTHCPHYS;2099 pVM->hmr0.s.vmx.HCPhysApicAccess = NIL_RTHCPHYS; 2100 pVM->hmr0.s.vmx.HCPhysVmreadBitmap = NIL_RTHCPHYS; 2101 pVM->hmr0.s.vmx.HCPhysVmwriteBitmap = NIL_RTHCPHYS; 2102 2102 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 2103 2103 { … … 3544 3544 if ( fGstVmwriteAll 3545 3545 || !VMXIsVmcsFieldReadOnly(VmcsField.u)) 3546 pVM->hm .s.vmx.paShadowVmcsFields[cRwFields++] = VmcsField.u;3546 pVM->hmr0.s.vmx.paShadowVmcsFields[cRwFields++] = VmcsField.u; 3547 3547 else 3548 pVM->hm .s.vmx.paShadowVmcsRoFields[cRoFields++] = VmcsField.u;3548 pVM->hmr0.s.vmx.paShadowVmcsRoFields[cRoFields++] = VmcsField.u; 3549 3549 } 3550 3550 } 3551 3551 3552 3552 /* Update the counts. */ 3553 pVM->hm .s.vmx.cShadowVmcsFields = cRwFields;3554 pVM->hm .s.vmx.cShadowVmcsRoFields = cRoFields;3553 pVM->hmr0.s.vmx.cShadowVmcsFields = cRwFields; 3554 pVM->hmr0.s.vmx.cShadowVmcsRoFields = cRoFields; 3555 3555 return VINF_SUCCESS; 3556 3556 } … … 3568 3568 */ 3569 3569 uint32_t const cbBitmap = X86_PAGE_4K_SIZE; 3570 uint8_t *pbVmreadBitmap = (uint8_t *)pVM->hm .s.vmx.pvVmreadBitmap;3571 uint8_t *pbVmwriteBitmap = (uint8_t *)pVM->hm .s.vmx.pvVmwriteBitmap;3570 uint8_t *pbVmreadBitmap = (uint8_t *)pVM->hmr0.s.vmx.pvVmreadBitmap; 3571 uint8_t *pbVmwriteBitmap = (uint8_t *)pVM->hmr0.s.vmx.pvVmwriteBitmap; 3572 3572 ASMMemFill32(pbVmreadBitmap, cbBitmap, UINT32_C(0xffffffff)); 3573 3573 ASMMemFill32(pbVmwriteBitmap, cbBitmap, UINT32_C(0xffffffff)); … … 3578 3578 */ 3579 3579 { 3580 uint32_t const *paShadowVmcsFields = pVM->hm .s.vmx.paShadowVmcsFields;3581 uint32_t const cShadowVmcsFields = pVM->hm .s.vmx.cShadowVmcsFields;3580 uint32_t const *paShadowVmcsFields = pVM->hmr0.s.vmx.paShadowVmcsFields; 3581 uint32_t const cShadowVmcsFields = pVM->hmr0.s.vmx.cShadowVmcsFields; 3582 3582 for (uint32_t i = 0; i < cShadowVmcsFields; i++) 3583 3583 { … … 3596 3596 if (pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL) 3597 3597 { 3598 uint32_t const *paShadowVmcsRoFields = pVM->hm .s.vmx.paShadowVmcsRoFields;3599 uint32_t const cShadowVmcsRoFields = pVM->hm .s.vmx.cShadowVmcsRoFields;3598 uint32_t const *paShadowVmcsRoFields = pVM->hmr0.s.vmx.paShadowVmcsRoFields; 3599 uint32_t const cShadowVmcsRoFields = pVM->hmr0.s.vmx.cShadowVmcsRoFields; 3600 3600 for (uint32_t i = 0; i < cShadowVmcsRoFields; i++) 3601 3601 { … … 3647 3647 DECLINLINE(void) hmR0VmxSetupVmcsApicAccessAddr(PVMCPUCC pVCpu) 3648 3648 { 3649 RTHCPHYS const HCPhysApicAccess = pVCpu->CTX_SUFF(pVM)->hm .s.vmx.HCPhysApicAccess;3649 RTHCPHYS const HCPhysApicAccess = pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.HCPhysApicAccess; 3650 3650 Assert(HCPhysApicAccess != NIL_RTHCPHYS); 3651 3651 Assert(!(HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */ … … 3663 3663 DECLINLINE(void) hmR0VmxSetupVmcsVmreadBitmapAddr(PVMCPUCC pVCpu) 3664 3664 { 3665 RTHCPHYS const HCPhysVmreadBitmap = pVCpu->CTX_SUFF(pVM)->hm .s.vmx.HCPhysVmreadBitmap;3665 RTHCPHYS const HCPhysVmreadBitmap = pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.HCPhysVmreadBitmap; 3666 3666 Assert(HCPhysVmreadBitmap != NIL_RTHCPHYS); 3667 3667 Assert(!(HCPhysVmreadBitmap & 0xfff)); /* Bits 11:0 MBZ. */ … … 3678 3678 DECLINLINE(void) hmR0VmxSetupVmcsVmwriteBitmapAddr(PVMCPUCC pVCpu) 3679 3679 { 3680 RTHCPHYS const HCPhysVmwriteBitmap = pVCpu->CTX_SUFF(pVM)->hm .s.vmx.HCPhysVmwriteBitmap;3680 RTHCPHYS const HCPhysVmwriteBitmap = pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.HCPhysVmwriteBitmap; 3681 3681 Assert(HCPhysVmwriteBitmap != NIL_RTHCPHYS); 3682 3682 Assert(!(HCPhysVmwriteBitmap & 0xfff)); /* Bits 11:0 MBZ. */ … … 4453 4453 /* Setup the crash dump page. */ 4454 4454 #ifdef VBOX_WITH_CRASHDUMP_MAGIC 4455 strcpy((char *)pVM->hm .s.vmx.pbScratch, "SCRATCH Magic");4456 *(uint64_t *)(pVM->hm .s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);4455 strcpy((char *)pVM->hmr0.s.vmx.pbScratch, "SCRATCH Magic"); 4456 *(uint64_t *)(pVM->hmr0.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef); 4457 4457 #endif 4458 4458 return VINF_SUCCESS; … … 4472 4472 4473 4473 #ifdef VBOX_WITH_CRASHDUMP_MAGIC 4474 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ) 4475 { 4476 Assert(pVM->hm.s.vmx.pvScratch); 4477 ASMMemZero32(pVM->hm.s.vmx.pvScratch, X86_PAGE_4K_SIZE); 4478 } 4474 if (pVM->hmr0.s.vmx.pbScratch) 4475 RT_BZERO(pVM->hmr0.s.vmx.pbScratch, X86_PAGE_4K_SIZE); 4479 4476 #endif 4480 4477 hmR0VmxStructsFree(pVM); … … 5436 5433 * like hardware errors. 5437 5434 */ 5438 uint32_t const cShadowVmcsFields = pVM->hm .s.vmx.cShadowVmcsFields;5435 uint32_t const cShadowVmcsFields = pVM->hmr0.s.vmx.cShadowVmcsFields; 5439 5436 for (uint32_t i = 0; i < cShadowVmcsFields; i++) 5440 5437 { 5441 5438 uint64_t u64Val; 5442 uint32_t const uVmcsField = pVM->hm .s.vmx.paShadowVmcsFields[i];5439 uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsFields[i]; 5443 5440 IEMReadVmxVmcsField(pVmcsNstGst, uVmcsField, &u64Val); 5444 5441 VMXWriteVmcs64(uVmcsField, u64Val); … … 5451 5448 if (pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL) 5452 5449 { 5453 uint32_t const cShadowVmcsRoFields = pVM->hm .s.vmx.cShadowVmcsRoFields;5450 uint32_t const cShadowVmcsRoFields = pVM->hmr0.s.vmx.cShadowVmcsRoFields; 5454 5451 for (uint32_t i = 0; i < cShadowVmcsRoFields; i++) 5455 5452 { 5456 5453 uint64_t u64Val; 5457 uint32_t const uVmcsField = pVM->hm .s.vmx.paShadowVmcsRoFields[i];5454 uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsRoFields[i]; 5458 5455 IEMReadVmxVmcsField(pVmcsNstGst, uVmcsField, &u64Val); 5459 5456 VMXWriteVmcs64(uVmcsField, u64Val); … … 5496 5493 * like hardware errors. 5497 5494 */ 5498 uint32_t const cShadowVmcsFields = pVM->hm .s.vmx.cShadowVmcsFields;5495 uint32_t const cShadowVmcsFields = pVM->hmr0.s.vmx.cShadowVmcsFields; 5499 5496 for (uint32_t i = 0; i < cShadowVmcsFields; i++) 5500 5497 { 5501 5498 uint64_t u64Val; 5502 uint32_t const uVmcsField = pVM->hm .s.vmx.paShadowVmcsFields[i];5499 uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsFields[i]; 5503 5500 VMXReadVmcs64(uVmcsField, &u64Val); 5504 5501 IEMWriteVmxVmcsField(pVmcsNstGst, uVmcsField, u64Val); … … 10243 10240 10244 10241 /* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */ 10245 Assert(pVM->hm .s.vmx.HCPhysApicAccess != NIL_RTHCPHYS);10246 rc = IOMR0MmioMapMmioHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm .s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);10242 Assert(pVM->hmr0.s.vmx.HCPhysApicAccess != NIL_RTHCPHYS); 10243 rc = IOMR0MmioMapMmioHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hmr0.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P); 10247 10244 AssertRCReturn(rc, rc); 10248 10245 -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r87522 r87531 1538 1538 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs); 1539 1539 1540 #ifdef TODO_9217_VMCSINFO 1540 1541 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess)); 1541 #ifdef TODO_9217_VMCSINFO1542 1542 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 1543 1543 { -
trunk/src/VBox/VMM/include/HMInternal.h
r87530 r87531 506 506 bool afPadding0; 507 507 508 /** Virtual address of the APIC-access page. */509 R0PTRTYPE(uint8_t *) pbApicAccess;510 /** Pointer to the VMREAD bitmap. */511 R0PTRTYPE(void *) pvVmreadBitmap;512 /** Pointer to the VMWRITE bitmap. */513 R0PTRTYPE(void *) pvVmwriteBitmap;514 515 /** Pointer to the shadow VMCS read-only fields array. */516 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;517 /** Pointer to the shadow VMCS read/write fields array. */518 R0PTRTYPE(uint32_t *) paShadowVmcsFields;519 /** Number of elements in the shadow VMCS read-only fields array. */520 uint32_t cShadowVmcsRoFields;521 /** Number of elements in the shadow VMCS read-write fields array. */522 uint32_t cShadowVmcsFields;523 524 508 /** Tagged-TLB flush type. */ 525 509 VMXTLBFLUSHTYPE enmTlbFlushType; … … 564 548 uint32_t u32Alignment1; 565 549 550 /** Host-physical address for a failing VMXON instruction. */ 551 RTHCPHYS HCPhysVmxEnableError; 552 566 553 /** VMX MSR values. */ 567 554 VMXMSRS Msrs; 568 555 569 /** Host-physical address for a failing VMXON instruction. */570 RTHCPHYS HCPhysVmxEnableError;571 /** Host-physical address of the APIC-access page. */572 RTHCPHYS HCPhysApicAccess;573 /** Host-physical address of the VMREAD bitmap. */574 RTHCPHYS HCPhysVmreadBitmap;575 /** Host-physical address of the VMWRITE bitmap. */576 RTHCPHYS HCPhysVmwriteBitmap;577 #ifdef VBOX_WITH_CRASHDUMP_MAGIC578 /** Host-physical address of the crash-dump scratch area. */579 RTHCPHYS HCPhysScratch;580 #endif581 582 #ifdef VBOX_WITH_CRASHDUMP_MAGIC583 /** Pointer to the crash-dump scratch bitmap. */584 R0PTRTYPE(uint8_t *) pbScratch;585 #endif586 556 /** Virtual address of the TSS page used for real mode emulation. */ 587 557 R3PTRTYPE(PVBOXTSS) pRealModeTSS; … … 679 649 struct HMR0VMXVM 680 650 { 651 /** Virtual address of the APIC-access page. */ 652 R0PTRTYPE(uint8_t *) pbApicAccess; 653 /** Pointer to the VMREAD bitmap. */ 654 R0PTRTYPE(void *) pvVmreadBitmap; 655 /** Pointer to the VMWRITE bitmap. */ 656 R0PTRTYPE(void *) pvVmwriteBitmap; 657 658 /** Pointer to the shadow VMCS read-only fields array. */ 659 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields; 660 /** Pointer to the shadow VMCS read/write fields array. */ 661 R0PTRTYPE(uint32_t *) paShadowVmcsFields; 662 /** Number of elements in the shadow VMCS read-only fields array. */ 663 uint32_t cShadowVmcsRoFields; 664 /** Number of elements in the shadow VMCS read-write fields array. */ 665 uint32_t cShadowVmcsFields; 666 667 /** Host-physical address of the APIC-access page. */ 668 RTHCPHYS HCPhysApicAccess; 669 /** Host-physical address of the VMREAD bitmap. */ 670 RTHCPHYS HCPhysVmreadBitmap; 671 /** Host-physical address of the VMWRITE bitmap. */ 672 RTHCPHYS HCPhysVmwriteBitmap; 673 674 #ifdef VBOX_WITH_CRASHDUMP_MAGIC 675 /** Host-physical address of the crash-dump scratch area. */ 676 RTHCPHYS HCPhysScratch; 677 /** Pointer to the crash-dump scratch bitmap. */ 678 R0PTRTYPE(uint8_t *) pbScratch; 679 #endif 680 681 681 /** Ring-0 memory object for per-VM VMX structures. */ 682 682 RTR0MEMOBJ hMemObj; 683 684 683 } vmx; 685 684
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