VirtualBox

Changeset 87541 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Feb 2, 2021 4:33:51 PM (4 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
142567
Message:

VMM/HMVMX: Use g_HmMsrs instead of pVM->hm.s.vmx.Msrs in ring-0, part 1. bugref:9217

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r87539 r87541  
    17171717    {
    17181718        /* Write the VMCS revision identifier to the VMXON region. */
    1719         *(uint32_t *)pvCpuPage = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
     1719        *(uint32_t *)pvCpuPage = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID);
    17201720    }
    17211721
    … …  
    20152015     * See Intel spec. Appendix A.1 "Basic VMX Information".
    20162016     */
    2017     uint32_t const cbVmcs = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_SIZE);
     2017    uint32_t const cbVmcs = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_SIZE);
    20182018    if (cbVmcs <= X86_PAGE_4K_SIZE)
    20192019    { /* likely */ }
    … …  
    29462946        if (pVM->hm.s.vmx.fVpid)
    29472947        {
    2948             bool fVpidFlush = RT_BOOL(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
     2948            bool fVpidFlush = RT_BOOL(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
    29492949            if (fVpidFlush)
    29502950            {
    … …  
    32983298    if (pVM->hmr0.s.fNestedPaging)
    32993299    {
    3300         if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
    3301         {
    3302             if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
     3300        if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
     3301        {
     3302            if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
    33033303                pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_SINGLE_CONTEXT;
    3304             else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
     3304            else if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
    33053305                pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_ALL_CONTEXTS;
    33063306            else
    … …  
    33133313
    33143314            /* Make sure the write-back cacheable memory type for EPT is supported. */
    3315             if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
     3315            if (RT_UNLIKELY(!(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
    33163316            {
    33173317                pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
    … …  
    33213321
    33223322            /* EPT requires a page-walk length of 4. */
    3323             if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
     3323            if (RT_UNLIKELY(!(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
    33243324            {
    33253325                pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
    … …  
    33423342    if (pVM->hm.s.vmx.fVpid)
    33433343    {
    3344         if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
    3345         {
    3346             if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
     3344        if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
     3345        {
     3346            if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
    33473347                pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_SINGLE_CONTEXT;
    3348             else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
     3348            else if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
    33493349                pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_ALL_CONTEXTS;
    33503350            else
    33513351            {
    33523352                /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
    3353                 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
     3353                if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
    33543354                    LogRelFunc(("Only INDIV_ADDR supported. Ignoring VPID.\n"));
    3355                 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
     3355                if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
    33563356                    LogRelFunc(("Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
    33573357                pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
    … …  
    35043504    bool const fGstVmwriteAll = pVM->cpum.ro.GuestFeatures.fVmxVmwriteAll;
    35053505    if (   !fGstVmwriteAll
    3506         || (pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL))
     3506        || (g_HmMsrs.u.vmx.u64Misc & VMX_MISC_VMWRITE_ALL))
    35073507    { /* likely. */ }
    35083508    else
    … …  
    35943594     * if the host supports VMWRITE to all supported VMCS fields.
    35953595     */
    3596     if (pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL)
     3596    if (g_HmMsrs.u.vmx.u64Misc & VMX_MISC_VMWRITE_ALL)
    35973597    {
    35983598        uint32_t const *paShadowVmcsRoFields = pVM->hmr0.s.vmx.paShadowVmcsRoFields;
    … …  
    42344234
    42354235    /* Set the CPU specified revision identifier at the beginning of the VMCS structure. */
    4236     PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    4237     *(uint32_t *)pVmcsInfo->pvVmcs = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
     4236    *(uint32_t *)pVmcsInfo->pvVmcs = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID);
    42384237    const char * const pszVmcs     = fIsNstGstVmcs ? "nested-guest VMCS" : "guest VMCS";
    42394238
    … …  
    42764275                            {
    42774276                                VMXVMCSREVID VmcsRevId;
    4278                                 VmcsRevId.u = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
     4277                                VmcsRevId.u = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID);
    42794278                                VmcsRevId.n.fIsShadowVmcs = 1;
    42804279                                *(uint32_t *)pVmcsInfo->pvShadowVmcs = VmcsRevId.u;
    … …  
    54455444         * VMCS fields, so the guest can VMREAD them without causing a VM-exit.
    54465445         */
    5447         if (pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL)
     5446        if (g_HmMsrs.u.vmx.u64Misc & VMX_MISC_VMWRITE_ALL)
    54485447        {
    54495448            uint32_t const cShadowVmcsRoFields = pVM->hmr0.s.vmx.cShadowVmcsRoFields;
    … …  
    56435642        PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
    56445643
    5645         uint64_t       fSetCr0 = pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
    5646         uint64_t const fZapCr0 = pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
     5644        uint64_t       fSetCr0 = g_HmMsrs.u.vmx.u64Cr0Fixed0;
     5645        uint64_t const fZapCr0 = g_HmMsrs.u.vmx.u64Cr0Fixed1;
    56475646        if (pVM->hm.s.vmx.fUnrestrictedGuest)
    56485647            fSetCr0 &= ~(uint64_t)(X86_CR0_PE | X86_CR0_PG);
    … …  
    58485847                         ("EPTP %#RX64\n", pVmcsInfo->HCPhysEPTP));
    58495848            AssertMsg(  !((pVmcsInfo->HCPhysEPTP >> 6) & 0x01)           /* Bit 6 (EPT accessed & dirty bit). */
    5850                       || (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
     5849                      || (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
    58515850                         ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVmcsInfo->HCPhysEPTP));
    58525851
    … …  
    59305929        PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
    59315930
    5932         uint64_t const fSetCr4 = pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
    5933         uint64_t const fZapCr4 = pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
     5931        uint64_t const fSetCr4 = g_HmMsrs.u.vmx.u64Cr4Fixed0;
     5932        uint64_t const fZapCr4 = g_HmMsrs.u.vmx.u64Cr4Fixed1;
    59345933
    59355934        /*
    … …  
    77647763                uint32_t const     cMsrs           = pVmcsInfo->cExitMsrStore;
    77657764                Assert(pMsrs);
    7766                 Assert(cMsrs <= VMX_MISC_MAX_MSRS(pVM->hm.s.vmx.Msrs.u64Misc));
     7765                Assert(cMsrs <= VMX_MISC_MAX_MSRS(g_HmMsrs.u.vmx.u64Misc));
    77677766                Assert(sizeof(*pMsrs) * cMsrs <= X86_PAGE_4K_SIZE);
    77687767                for (uint32_t i = 0; i < cMsrs; i++)
    … …  
    96939692         */
    96949693        /** @todo Why do we need to OR and AND the fixed-0 and fixed-1 bits below? */
    9695         uint64_t       fSetCr0 = (pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
    9696         uint64_t const fZapCr0 = (pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
     9694        uint64_t       fSetCr0 = (g_HmMsrs.u.vmx.u64Cr0Fixed0 & g_HmMsrs.u.vmx.u64Cr0Fixed1);
     9695        uint64_t const fZapCr0 = (g_HmMsrs.u.vmx.u64Cr0Fixed0 | g_HmMsrs.u.vmx.u64Cr0Fixed1);
    96979696        /* Exceptions for unrestricted guest execution for CR0 fixed bits (PE, PG).
    96989697           See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
    … …  
    97149713         */
    97159714        /** @todo Why do we need to OR and AND the fixed-0 and fixed-1 bits below? */
    9716         uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
    9717         uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
     9715        uint64_t const fSetCr4 = (g_HmMsrs.u.vmx.u64Cr4Fixed0 & g_HmMsrs.u.vmx.u64Cr4Fixed1);
     9716        uint64_t const fZapCr4 = (g_HmMsrs.u.vmx.u64Cr4Fixed0 | g_HmMsrs.u.vmx.u64Cr4Fixed1);
    97189717
    97199718        uint64_t u64GuestCr4;
    … …  
    1008810087        AssertRC(rc);
    1008910088        HMVMX_CHECK_BREAK(   !u32ActivityState
    10090                           || (u32ActivityState & RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
     10089                          || (u32ActivityState & RT_BF_GET(g_HmMsrs.u.vmx.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
    1009110090                             VMX_IGS_ACTIVITY_STATE_INVALID);
    1009210091        HMVMX_CHECK_BREAK(   !(pCtx->ss.Attr.n.u2Dpl)
    … …  
    1017110170            VMXVMCSREVID VmcsRevId;
    1017210171            VmcsRevId.u = *(uint32_t *)pVmcsInfo->pvShadowVmcs;
    10173             HMVMX_CHECK_BREAK(VmcsRevId.n.u31RevisionId == RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID),
     10172            HMVMX_CHECK_BREAK(VmcsRevId.n.u31RevisionId == RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID),
    1017410173                              VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID);
    1017510174            HMVMX_CHECK_BREAK(VmcsRevId.n.fIsShadowVmcs == (uint32_t)!!(pVmcsInfo->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING),
    … …  
    1566815667            Log4Func(("cs:rip=%#04x:%#RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
    1566915668            AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
    15670             bool const fInsOutsInfo = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
     15669            bool const fInsOutsInfo = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
    1567115670            if (fInsOutsInfo)
    1567215671            {
    … …  
    1714017139            if (fVmxInsOutsInfo)
    1714117140            {
    17142                 Assert(RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS)); /* Paranoia. */
     17141                Assert(RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS)); /* Paranoia. */
    1714317142                hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
    1714417143            }
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