Changeset 87558 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Feb 3, 2021 11:21:28 AM (4 years ago)
- File:
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- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r87557 r87558 875 875 * @remarks Must only be called when LBR is enabled. 876 876 */ 877 DECL_FORCE_INLINE(bool) hmR0VmxIsLbrBranchFromMsr(PCVM pVM, uint32_t idMsr, uint32_t *pidxMsr)878 { 879 Assert(pVM->hm .s.vmx.fLbr);880 Assert(pVM->hm .s.vmx.idLbrFromIpMsrFirst);881 uint32_t const cLbrStack = pVM->hm .s.vmx.idLbrFromIpMsrLast - pVM->hm.s.vmx.idLbrFromIpMsrFirst + 1;882 uint32_t const idxMsr = idMsr - pVM->hm .s.vmx.idLbrFromIpMsrFirst;877 DECL_FORCE_INLINE(bool) hmR0VmxIsLbrBranchFromMsr(PCVMCC pVM, uint32_t idMsr, uint32_t *pidxMsr) 878 { 879 Assert(pVM->hmr0.s.vmx.fLbr); 880 Assert(pVM->hmr0.s.vmx.idLbrFromIpMsrFirst); 881 uint32_t const cLbrStack = pVM->hmr0.s.vmx.idLbrFromIpMsrLast - pVM->hmr0.s.vmx.idLbrFromIpMsrFirst + 1; 882 uint32_t const idxMsr = idMsr - pVM->hmr0.s.vmx.idLbrFromIpMsrFirst; 883 883 if (idxMsr < cLbrStack) 884 884 { … … 903 903 * are supported by the CPU (see hmR0VmxSetupLbrMsrRange). 904 904 */ 905 DECL_FORCE_INLINE(bool) hmR0VmxIsLbrBranchToMsr(PCVM pVM, uint32_t idMsr, uint32_t *pidxMsr)906 { 907 Assert(pVM->hm .s.vmx.fLbr);908 if (pVM->hm .s.vmx.idLbrToIpMsrFirst)909 { 910 uint32_t const cLbrStack = pVM->hm .s.vmx.idLbrToIpMsrLast - pVM->hm.s.vmx.idLbrToIpMsrFirst + 1;911 uint32_t const idxMsr = idMsr - pVM->hm .s.vmx.idLbrToIpMsrFirst;905 DECL_FORCE_INLINE(bool) hmR0VmxIsLbrBranchToMsr(PCVMCC pVM, uint32_t idMsr, uint32_t *pidxMsr) 906 { 907 Assert(pVM->hmr0.s.vmx.fLbr); 908 if (pVM->hmr0.s.vmx.idLbrToIpMsrFirst) 909 { 910 uint32_t const cLbrStack = pVM->hmr0.s.vmx.idLbrToIpMsrLast - pVM->hmr0.s.vmx.idLbrToIpMsrFirst + 1; 911 uint32_t const idxMsr = idMsr - pVM->hmr0.s.vmx.idLbrToIpMsrFirst; 912 912 if (idxMsr < cLbrStack) 913 913 { … … 2796 2796 { 2797 2797 /* Verify LBR MSRs (used only for debugging) are intercepted. We don't passthru these MSRs to the guest yet. */ 2798 PCVM pVM = pVCpu->CTX_SUFF(pVM);2799 if ( pVM->hm .s.vmx.fLbr2798 PCVMCC pVM = pVCpu->CTX_SUFF(pVM); 2799 if ( pVM->hmr0.s.vmx.fLbr 2800 2800 && ( hmR0VmxIsLbrBranchFromMsr(pVM, pGuestMsrLoad->u32Msr, NULL /* pidxMsr */) 2801 2801 || hmR0VmxIsLbrBranchToMsr(pVM, pGuestMsrLoad->u32Msr, NULL /* pidxMsr */) 2802 || pGuestMsrLoad->u32Msr == pVM->hm .s.vmx.idLbrTosMsr))2802 || pGuestMsrLoad->u32Msr == pVM->hmr0.s.vmx.idLbrTosMsr)) 2803 2803 { 2804 2804 AssertMsgReturnVoid((fMsrpm & VMXMSRPM_MASK) == VMXMSRPM_EXIT_RD_WR, … … 3396 3396 static int hmR0VmxSetupLbrMsrRange(PVMCC pVM) 3397 3397 { 3398 Assert(pVM->hm .s.vmx.fLbr);3398 Assert(pVM->hmr0.s.vmx.fLbr); 3399 3399 uint32_t idLbrFromIpMsrFirst; 3400 3400 uint32_t idLbrFromIpMsrLast; … … 3481 3481 * Update the LBR info. to the VM struct. for use later. 3482 3482 */ 3483 pVM->hm.s.vmx.idLbrTosMsr = idLbrTosMsr; 3484 pVM->hm.s.vmx.idLbrFromIpMsrFirst = idLbrFromIpMsrFirst; 3485 pVM->hm.s.vmx.idLbrFromIpMsrLast = idLbrFromIpMsrLast; 3486 3487 pVM->hm.s.vmx.idLbrToIpMsrFirst = idLbrToIpMsrFirst; 3488 pVM->hm.s.vmx.idLbrToIpMsrLast = idLbrToIpMsrLast; 3483 pVM->hmr0.s.vmx.idLbrTosMsr = idLbrTosMsr; 3484 3485 pVM->hm.s.vmx.idLbrFromIpMsrFirstForRing3 = pVM->hmr0.s.vmx.idLbrFromIpMsrFirst = idLbrFromIpMsrFirst; 3486 pVM->hm.s.vmx.idLbrFromIpMsrLastForRing3 = pVM->hmr0.s.vmx.idLbrFromIpMsrLast = idLbrFromIpMsrLast; 3487 3488 pVM->hm.s.vmx.idLbrToIpMsrFirstForRing3 = pVM->hmr0.s.vmx.idLbrToIpMsrFirst = idLbrToIpMsrFirst; 3489 pVM->hm.s.vmx.idLbrToIpMsrLastForRing3 = pVM->hmr0.s.vmx.idLbrToIpMsrLast = idLbrToIpMsrLast; 3489 3490 return VINF_SUCCESS; 3490 3491 } … … 4073 4074 pVmcsInfo->u64Cr4Mask = u64Cr4Mask; 4074 4075 4075 if (pVCpu->CTX_SUFF(pVM)->hm .s.vmx.fLbr)4076 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fLbr) 4076 4077 { 4077 4078 rc = VMXWriteVmcsNw(VMX_VMCS64_GUEST_DEBUGCTL_FULL, MSR_IA32_DEBUGCTL_LBR); … … 4549 4550 4550 4551 /* Determine LBR capabilities. */ 4551 if (pVM->hm.s.vmx.fLbr) 4552 pVM->hmr0.s.vmx.fLbr = pVM->hm.s.vmx.fLbrCfg; 4553 if (pVM->hmr0.s.vmx.fLbr) 4552 4554 { 4553 4555 rc = hmR0VmxSetupLbrMsrRange(pVM); … … 6834 6836 6835 6837 /* Last Branch Record. */ 6836 if (pVM->hm .s.vmx.fLbr)6838 if (pVM->hmr0.s.vmx.fLbr) 6837 6839 { 6838 6840 PVMXVMCSINFOSHARED const pVmcsInfoShared = pVmxTransient->pVmcsInfo->pShared; 6839 uint32_t const idFromIpMsrStart = pVM->hm .s.vmx.idLbrFromIpMsrFirst;6840 uint32_t const idToIpMsrStart = pVM->hm .s.vmx.idLbrToIpMsrFirst;6841 uint32_t const cLbrStack = pVM->hm .s.vmx.idLbrFromIpMsrLast - pVM->hm.s.vmx.idLbrFromIpMsrFirst + 1;6841 uint32_t const idFromIpMsrStart = pVM->hmr0.s.vmx.idLbrFromIpMsrFirst; 6842 uint32_t const idToIpMsrStart = pVM->hmr0.s.vmx.idLbrToIpMsrFirst; 6843 uint32_t const cLbrStack = pVM->hmr0.s.vmx.idLbrFromIpMsrLast - pVM->hmr0.s.vmx.idLbrFromIpMsrFirst + 1; 6842 6844 Assert(cLbrStack <= 32); 6843 6845 for (uint32_t i = 0; i < cLbrStack; i++) … … 6859 6861 6860 6862 /* Add LBR top-of-stack MSR (which contains the index to the most recent record). */ 6861 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, pVM->hm .s.vmx.idLbrTosMsr,6863 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, pVM->hmr0.s.vmx.idLbrTosMsr, 6862 6864 pVmcsInfoShared->u64LbrTosMsr, false /* fSetReadWrite */, 6863 6865 false /* fUpdateHostMsr */); … … 7784 7786 { 7785 7787 uint32_t idxLbrMsr; 7786 if (pVM->hm .s.vmx.fLbr)7788 if (pVM->hmr0.s.vmx.fLbr) 7787 7789 { 7788 7790 if (hmR0VmxIsLbrBranchFromMsr(pVM, idMsr, &idxLbrMsr)) … … 7798 7800 break; 7799 7801 } 7800 if (idMsr == pVM->hm .s.vmx.idLbrTosMsr)7802 if (idMsr == pVM->hmr0.s.vmx.idLbrTosMsr) 7801 7803 { 7802 7804 pVmcsInfoShared->u64LbrTosMsr = pMsrs[i].u64Value;
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