Changeset 87563 in vbox for trunk/src/VBox/VMM/include
- Timestamp:
- Feb 3, 2021 1:23:13 PM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 142590
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/include/HMInternal.h
r87562 r87563 440 440 bool afAlignment1[5]; 441 441 442 /** @todo r=bird: for better cache locality for SVM, it would be good to split443 * out the non-esssential data (i.e config and for-ring3 bits). */444 442 struct 445 443 { … … 450 448 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */ 451 449 uint8_t cPreemptTimerShift; 452 bool afAlignment1[5]; 453 454 /** Pause-loop exiting (PLE) gap in ticks. */ 455 uint32_t cPleGapTicks; 456 /** Pause-loop exiting (PLE) window in ticks. */ 457 uint32_t cPleWindowTicks; 458 459 /** Virtual address of the TSS page used for real mode emulation. */ 460 R3PTRTYPE(PVBOXTSS) pRealModeTSS; 461 /** Virtual address of the identity page table used for real mode and protected 462 * mode without paging emulation in EPT mode. */ 463 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable; 450 bool fAlignment1; 464 451 465 452 /** @name Configuration (gets copied if problematic) … … 477 464 /** @} */ 478 465 479 /** @name For ring-3 consumption 480 * @{ */ 481 /** Set if VPID is supported (ring-3 copy). */ 482 bool fVpidForRing3; 483 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX 484 * init, for logging). */ 485 bool fSupportsVmcsEferForRing3; 486 /** Whether to use VMCS shadowing. */ 487 bool fUseVmcsShadowingForRing3; 488 bool fAlignment2; 489 490 /** Host CR4 value (set by ring-0 VMX init, for logging). */ 491 uint64_t u64HostCr4ForRing3; 492 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */ 493 uint64_t u64HostSmmMonitorCtlForRing3; 494 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */ 495 uint64_t u64HostMsrEferForRing3; 496 497 /** The first valid host LBR branch-from-IP stack range. */ 498 uint32_t idLbrFromIpMsrFirstForRing3; 499 /** The last valid host LBR branch-from-IP stack range. */ 500 uint32_t idLbrFromIpMsrLastForRing3; 501 502 /** The first valid host LBR branch-to-IP stack range. */ 503 uint32_t idLbrToIpMsrFirstForRing3; 504 /** The last valid host LBR branch-to-IP stack range. */ 505 uint32_t idLbrToIpMsrLastForRing3; 506 507 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */ 508 RTHCPHYS HCPhysVmxEnableError; 509 /** VMX MSR values (only for ring-3 consumption). */ 510 VMXMSRS MsrsForRing3; 511 512 /** Tagged-TLB flush type (only for ring-3 consumption). */ 513 VMXTLBFLUSHTYPE enmTlbFlushTypeForRing3; 514 /** Flush type to use for INVEPT (only for ring-3 consumption). */ 515 VMXTLBFLUSHEPT enmTlbFlushEptForRing3; 516 /** Flush type to use for INVVPID (only for ring-3 consumption). */ 517 VMXTLBFLUSHVPID enmTlbFlushVpidForRing3; 518 /** @} */ 466 /** Pause-loop exiting (PLE) gap in ticks. */ 467 uint32_t cPleGapTicks; 468 /** Pause-loop exiting (PLE) window in ticks. */ 469 uint32_t cPleWindowTicks; 470 471 /** Virtual address of the TSS page used for real mode emulation. */ 472 R3PTRTYPE(PVBOXTSS) pRealModeTSS; 473 /** Virtual address of the identity page table used for real mode and protected 474 * mode without paging emulation in EPT mode. */ 475 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable; 519 476 } vmx; 520 477 … … 541 498 uint16_t cPauseFilterThresholdTicks; 542 499 uint32_t u32Alignment2; 543 544 /** @name For ring-3 consumption545 * @{ */546 /** SVM revision. */547 uint32_t u32Rev;548 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */549 uint32_t fFeaturesForRing3;550 /** HWCR MSR (for diagnostics). */551 uint64_t u64MsrHwcr;552 /** @} */553 500 } svm; 554 501 … … 566 513 /** Size of the guest patch memory block. */ 567 514 uint32_t cbGuestPatchMem; 568 569 /** Last recorded error code during HM ring-0 init. */ 570 int32_t rcInit; 571 572 /** Maximum ASID allowed. 573 * This is mainly for the release log. */ 574 uint32_t uMaxAsidForLog; 575 /** World switcher flags (HM_WSF_XXX) for the release log. */ 576 uint32_t fWorldSwitcherForLog; 515 uint32_t u32Alignment2; 516 517 /** For ring-3 use only. */ 518 struct 519 { 520 /** Last recorded error code during HM ring-0 init. */ 521 int32_t rcInit; 522 uint32_t u32Alignment3; 523 524 /** Maximum ASID allowed. 525 * This is mainly for the release log. */ 526 uint32_t uMaxAsid; 527 /** World switcher flags (HM_WSF_XXX) for the release log. */ 528 uint32_t fWorldSwitcher; 529 530 struct 531 { 532 /** Set if VPID is supported (ring-3 copy). */ 533 bool fVpid; 534 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX 535 * init, for logging). */ 536 bool fSupportsVmcsEfer; 537 /** Whether to use VMCS shadowing. */ 538 bool fUseVmcsShadowing; 539 bool fAlignment2; 540 541 /** Host CR4 value (set by ring-0 VMX init, for logging). */ 542 uint64_t u64HostCr4; 543 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */ 544 uint64_t u64HostSmmMonitorCtl; 545 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */ 546 uint64_t u64HostMsrEfer; 547 548 /** The first valid host LBR branch-from-IP stack range. */ 549 uint32_t idLbrFromIpMsrFirst; 550 /** The last valid host LBR branch-from-IP stack range. */ 551 uint32_t idLbrFromIpMsrLast; 552 553 /** The first valid host LBR branch-to-IP stack range. */ 554 uint32_t idLbrToIpMsrFirst; 555 /** The last valid host LBR branch-to-IP stack range. */ 556 uint32_t idLbrToIpMsrLast; 557 558 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */ 559 RTHCPHYS HCPhysVmxEnableError; 560 /** VMX MSR values (only for ring-3 consumption). */ 561 VMXMSRS Msrs; 562 563 /** Tagged-TLB flush type (only for ring-3 consumption). */ 564 VMXTLBFLUSHTYPE enmTlbFlushType; 565 /** Flush type to use for INVEPT (only for ring-3 consumption). */ 566 VMXTLBFLUSHEPT enmTlbFlushEpt; 567 /** Flush type to use for INVVPID (only for ring-3 consumption). */ 568 VMXTLBFLUSHVPID enmTlbFlushVpid; 569 } vmx; 570 571 struct 572 { 573 /** SVM revision. */ 574 uint32_t u32Rev; 575 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */ 576 uint32_t fFeatures; 577 /** HWCR MSR (for diagnostics). */ 578 uint64_t u64MsrHwcr; 579 } svm; 580 } ForR3; 577 581 578 582 /** @name Configuration not used (much) after VM setup … … 637 641 AssertCompileMemberAlignment(HM, vmx, 8); 638 642 AssertCompileMemberAlignment(HM, svm, 8); 643 AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8); 644 AssertCompile(RTASSERT_OFFSET_OF(HM, PatchTree) <= 64); /* First cache line has the essentials for both VT-x and SVM operation. */ 639 645 640 646
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