Changeset 87564 in vbox for trunk/src/VBox/VMM

Timestamp:

Feb 3, 2021 1:32:10 PM (4 years ago)

Author:

vboxsync

Message:

VMM/HM: Did some reshuffling in HMR0PERVM. bugref:9217

Location:

trunk/src/VBox/VMM

Files:

• VMMR0/HMVMXR0.cpp (modified) (2 diffs)
• include/HMInternal.h (modified) (5 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -3659 +3659 @@
 }
 
-
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+
 /**
  * Sets up the VMREAD bitmap address for the VMCS.
@@ -3689 +3689 @@
     AssertRC(rc);
 }
+
 #endif
-
 
 /**

trunk/src/VBox/VMM/include/HMInternal.h

@@ -650 +650 @@
 typedef struct HMR0PERVM
 {
+    /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
+     * This number is set much higher when RTThreadPreemptIsPending is reliable. */
+    uint32_t                    cMaxResumeLoops;
+
     /** Set if nested paging is enabled. */
     bool                        fNestedPaging;
     /** Set if we can support 64-bit guests or not. */
     bool                        fAllow64BitGuests;
-    bool                        afAlignment0[2];
-
-    /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
-     * This number is set much higher when RTThreadPreemptIsPending is reliable. */
-    uint32_t                    cMaxResumeLoops;
+    bool                        afAlignment1[1];
+
+    /** AMD-V specific data. */
+    struct HMR0SVMVM
+    {
+        /** Set if erratum 170 affects the AMD cpu. */
+        bool                        fAlwaysFlushTLB;
+    } svm;
 
     /** VT-x specific data. */
@@ -672 +679 @@
         /** Set if Last Branch Record (LBR) is enabled. */
         bool                        fLbr;
+        bool                        afAlignment2[3];
+
         /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
         bool                        fVpid;
@@ -681 +690 @@
         VMXTLBFLUSHVPID             enmTlbFlushVpid;
 
+        /** The host LBR TOS (top-of-stack) MSR id. */
+        uint32_t                    idLbrTosMsr;
+
         /** The first valid host LBR branch-from-IP stack range. */
         uint32_t                    idLbrFromIpMsrFirst;
@@ -691 +703 @@
         uint32_t                    idLbrToIpMsrLast;
 
-        /** The host LBR TOS (top-of-stack) MSR id. */
-        uint32_t                    idLbrTosMsr;
-        uint32_t                    u32Alignment1;
-
-        /** Virtual address of the APIC-access page. */
-        R0PTRTYPE(uint8_t *)        pbApicAccess;
         /** Pointer to the VMREAD bitmap. */
         R0PTRTYPE(void *)           pvVmreadBitmap;
@@ -727 +733 @@
         /** Ring-0 memory object for per-VM VMX structures. */
         RTR0MEMOBJ                  hMemObj;
+        /** Virtual address of the APIC-access page (not used). */
+        R0PTRTYPE(uint8_t *)        pbApicAccess;
     } vmx;
-
-    /** AMD-V specific data. */
-    struct HMR0SVMVM
-    {
-        /** Set if erratum 170 affects the AMD cpu. */
-        bool                        fAlwaysFlushTLB;
-        bool                        afAlignment0[3];
-    } svm;
 } HMR0PERVM;
 /** Pointer to HM's per-VM ring-0 instance data. */