Changeset 87704 in vbox for trunk/src/VBox/HostDrivers/Support

Timestamp:

Feb 10, 2021 11:59:11 PM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

142748

Message:

SUPDrv: Build fix for older kernels. bugref:9937

File:

• trunk/src/VBox/HostDrivers/Support/SUPDrvInternal.h (modified) (1 diff)

trunk/src/VBox/HostDrivers/Support/SUPDrvInternal.h

@@ -87 +87 @@
 #       include <linux/timer.h>
 #   endif
-#   if RTLNX_VER_MIN(3,2,0)
+#   if RTLNX_VER_MIN(3,2,0) && defined(SUPDRV_AGNOSTIC)
 #       include <linux/export.h>
 #   else
 #       include <linux/module.h>
+#       if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) /* fix conflicts with iprt/x86.h */
+#           undef CS
+#           undef SS
+#           undef EFLAGS
+#           undef R15
+#           undef R14
+#           undef R13
+#           undef R12
+#           undef R11
+#           undef R10
+#           undef R9
+#           undef R8
+#           undef RDI
+#           undef RSI
+#           undef RBP
+#           undef RSP
+#           undef RBX
+#           undef RDX
+#           undef RCX
+#           undef RAX
+#           undef MSR_CORE_PERF_LIMIT_REASONS
+#           undef MSR_DRAM_ENERGY_STATUS
+#           undef MSR_DRAM_PERF_STATUS
+#           undef MSR_DRAM_POWER_INFO
+#           undef MSR_DRAM_POWER_LIMIT
+#           undef MSR_IA32_APERF
+#           undef MSR_IA32_ARCH_CAPABILITIES
+#           undef MSR_IA32_CR_PAT
+#           undef MSR_IA32_DS_AREA
+#           undef MSR_IA32_FEATURE_CONTROL
+#           undef MSR_IA32_FLUSH_CMD
+#           undef MSR_IA32_MC0_CTL
+#           undef MSR_IA32_MC0_STATUS
+#           undef MSR_IA32_MCG_CAP
+#           undef MSR_IA32_MCG_STATUS
+#           undef MSR_IA32_MISC_ENABLE
+#           undef MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
+#           undef MSR_IA32_MISC_ENABLE_LIMIT_CPUID
+#           undef MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
+#           undef MSR_IA32_MISC_ENABLE_TCC
+#           undef MSR_IA32_MISC_ENABLE_XD_DISABLE
+#           undef MSR_IA32_MPERF
+#           undef MSR_IA32_PEBS_ENABLE
+#           undef MSR_IA32_PERF_CTL
+#           undef MSR_IA32_PERF_STATUS
+#           undef MSR_IA32_PLATFORM_ID
+#           undef MSR_IA32_PMC0
+#           undef MSR_IA32_PRED_CMD
+#           undef MSR_IA32_RTIT_CTL
+#           undef MSR_IA32_SMBASE
+#           undef MSR_IA32_SMM_MONITOR_CTL
+#           undef MSR_IA32_SPEC_CTRL
+#           undef MSR_IA32_THERM_STATUS
+#           undef MSR_IA32_TSC
+#           undef MSR_IA32_TSC_ADJUST
+#           undef MSR_IA32_TSX_CTRL
+#           undef MSR_IA32_VMX_BASIC
+#           undef MSR_IA32_VMX_CR0_FIXED0
+#           undef MSR_IA32_VMX_CR0_FIXED1
+#           undef MSR_IA32_VMX_CR4_FIXED0
+#           undef MSR_IA32_VMX_CR4_FIXED1
+#           undef MSR_IA32_VMX_ENTRY_CTLS
+#           undef MSR_IA32_VMX_EPT_VPID_CAP
+#           undef MSR_IA32_VMX_EXIT_CTLS
+#           undef MSR_IA32_VMX_MISC
+#           undef MSR_IA32_VMX_PINBASED_CTLS
+#           undef MSR_IA32_VMX_PROCBASED_CTLS
+#           undef MSR_IA32_VMX_PROCBASED_CTLS2
+#           undef MSR_IA32_VMX_TRUE_ENTRY_CTLS
+#           undef MSR_IA32_VMX_TRUE_EXIT_CTLS
+#           undef MSR_IA32_VMX_TRUE_PINBASED_CTLS
+#           undef MSR_IA32_VMX_TRUE_PROCBASED_CTLS
+#           undef MSR_IA32_VMX_VMCS_ENUM
+#           undef MSR_IA32_VMX_VMFUNC
+#           undef MSR_K6_PFIR
+#           undef MSR_K6_PSOR
+#           undef MSR_K6_UWCCR
+#           undef MSR_K6_WHCR
+#           undef MSR_K7_EVNTSEL0
+#           undef MSR_K7_EVNTSEL1
+#           undef MSR_K7_EVNTSEL2
+#           undef MSR_K7_EVNTSEL3
+#           undef MSR_K7_PERFCTR0
+#           undef MSR_K7_PERFCTR1
+#           undef MSR_K7_PERFCTR2
+#           undef MSR_K7_PERFCTR3
+#           undef MSR_K8_SYSCFG
+#           undef MSR_K8_TOP_MEM1
+#           undef MSR_K8_TOP_MEM2
+#           undef MSR_OFFCORE_RSP_0
+#           undef MSR_OFFCORE_RSP_1
+#           undef MSR_PKG_C10_RESIDENCY
+#           undef MSR_PKG_C2_RESIDENCY
+#           undef MSR_PKG_CST_CONFIG_CONTROL
+#           undef MSR_PKG_ENERGY_STATUS
+#           undef MSR_PKG_PERF_STATUS
+#           undef MSR_PKG_POWER_INFO
+#           undef MSR_PKG_POWER_LIMIT
+#           undef MSR_PKGC3_IRTL
+#           undef MSR_PP0_ENERGY_STATUS
+#           undef MSR_PP1_ENERGY_STATUS
+#           undef MSR_RAPL_POWER_UNIT
+#           undef MSR_TURBO_ACTIVATION_RATIO
+#           undef VMX_BASIC_MEM_TYPE_WB
+#           undef X86_CR0_AM
+#           undef X86_CR0_CD
+#           undef X86_CR0_EM
+#           undef X86_CR0_ET
+#           undef X86_CR0_MP
+#           undef X86_CR0_NE
+#           undef X86_CR0_NW
+#           undef X86_CR0_PE
+#           undef X86_CR0_PG
+#           undef X86_CR0_TS
+#           undef X86_CR0_WP
+#           undef X86_CR3_PCD
+#           undef X86_CR3_PWT
+#           undef X86_CR4_DE
+#           undef X86_CR4_FSGSBASE
+#           undef X86_CR4_MCE
+#           undef X86_CR4_OSFXSR
+#           undef X86_CR4_OSXSAVE
+#           undef X86_CR4_PAE
+#           undef X86_CR4_PCE
+#           undef X86_CR4_PCIDE
+#           undef X86_CR4_PGE
+#           undef X86_CR4_PKE
+#           undef X86_CR4_PSE
+#           undef X86_CR4_PVI
+#           undef X86_CR4_SMAP
+#           undef X86_CR4_SMEP
+#           undef X86_CR4_SMXE
+#           undef X86_CR4_TSD
+#           undef X86_CR4_UMIP
+#           undef X86_CR4_VME
+#           undef X86_CR4_VMXE
+#       endif
 #   endif
 #   define SUPR0_EXPORT_SYMBOL(a_Name) EXPORT_SYMBOL(a_Name)