Changeset 87752 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Feb 13, 2021 2:13:15 PM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

142804

Message:

VMM/HM: Don't use ordered writes for pVCpu->hm.s.fCheckedTLBFlush as it's only ever checked together with cWorldSwitchExits by hmR0PokeCpu, and cWorldSwitchExits is written atomically right afterwards. Both variables are only updated by the EMT owning them. bugref:9941

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMSVMR0.cpp (modified) (3 diffs)
• HMVMXR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -1306 +1306 @@
 
     /* Set TLB flush state as checked until we return from the world switch. */
-    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
+    ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
 
     /* Check for explicit TLB flushes. */
@@ -4273 +4273 @@
 #endif
 
-    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);    /* Used for TLB flushing, set this across the world switch. */
+    ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);  /* Used for TLB flushing, set this across the world switch. */
     /* Flush the appropriate tagged-TLB entries. */
     hmR0SvmFlushTaggedTlb(pHostCpu,  pVCpu, pVmcb);
@@ -4351 +4351 @@
 
     uint64_t const uHostTsc = ASMReadTSC();                     /* Read the TSC as soon as possible. */
-    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);   /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
+    ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
     ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits);          /* Initialized in vmR3CreateUVM(): used for EMT poking. */
 

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -11088 +11088 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
 
-    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);    /* Used for TLB flushing, set this across the world switch. */
+    ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);  /* Used for TLB flushing, set this across the world switch. */
     hmR0VmxFlushTaggedTlb(pHostCpu, pVCpu, pVmcsInfo);          /* Invalidate the appropriate guest entries from the TLB. */
     Assert(idCurrentCpu == pVCpu->hmr0.s.idLastCpu);
@@ -11155 +11155 @@
     uint64_t const uHostTsc = ASMReadTSC();                     /** @todo We can do a lot better here, see @bugref{9180#c38}. */
 
-    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);   /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
+    ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
     ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits);          /* Initialized in vmR3CreateUVM(): used for EMT poking. */
     pVCpu->hm.s.fCtxChanged            = 0;                     /* Exits/longjmps to ring-3 requires saving the guest state. */