Changeset 87834 in vbox for trunk/src/VBox/Devices/Bus
- Timestamp:
- Feb 22, 2021 3:26:40 PM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 142898
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r87828 r87834 351 351 /** The event semaphore the command thread waits on. */ 352 352 SUPSEMEVENT hEvtCmdThread; 353 /** Whether the command thread has been signaled for wake up. */ 354 bool volatile fCmdThreadSignaled; 355 /** Padding. */ 356 bool afPadding0[7]; 353 357 354 358 #ifdef IOMMU_WITH_DTE_CACHE … … 565 569 /** The command thread handle. */ 566 570 R3PTRTYPE(PPDMTHREAD) pCmdThread; 567 /** Whether the command thread is sleeping. */568 bool volatile fCmdThreadSleeping;569 /** Whether the command thread has been signaled for wake up. */570 bool volatile fCmdThreadSignaled;571 /** Alignment padding. */572 uint8_t afPadding0[6];573 571 #ifdef IOMMU_WITH_IOTLBE_CACHE 574 572 /** Pointer to array of pre-allocated IOTLBEs. */ … … 1296 1294 { 1297 1295 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 1298 PIOMMU CCpThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);1296 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 1299 1297 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis); 1300 1298 … … 1659 1657 1660 1658 /** 1661 * Wakes up the command thread if there are commands to be processed or if 1662 * processing is requested to be stopped by software. 1659 * Wakes up the command thread if there are commands to be processed. 1663 1660 * 1664 1661 * @param pDevIns The IOMMU device instance. … … 1670 1667 Log4Func(("\n")); 1671 1668 1672 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 1673 if (pThis->Status.n.u1CmdBufRunning) 1669 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 1670 if ( pThis->Status.n.u1CmdBufRunning 1671 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off 1672 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)) 1674 1673 { 1675 1674 Log4Func(("Signaling command thread\n")); … … 2136 2135 LogFunc(("Command buffer enabled\n")); 2137 2136 2138 /* Wake up the command thread to start processing commands . */2137 /* Wake up the command thread to start processing commands if any. */ 2139 2138 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns); 2140 2139 } … … 4768 4767 { 4769 4768 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 4770 PIOMMU CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);4769 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 4771 4770 4772 4771 STAM_COUNTER_INC(&pThis->StatCmd); … … 4803 4802 if (pCmdComWait->n.u1Interrupt) 4804 4803 { 4805 IOMMU_LOCK(pDevIns, pThis CC);4804 IOMMU_LOCK(pDevIns, pThisR3); 4806 4805 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR); 4807 4806 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn; 4808 IOMMU_UNLOCK(pDevIns, pThis CC);4807 IOMMU_UNLOCK(pDevIns, pThisR3); 4809 4808 4810 4809 if (fRaiseInt) … … 4998 4997 { 4999 4998 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 5000 PIOMMU CC pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);4999 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 5001 5000 5002 5001 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING) … … 5017 5016 * Sleep perpetually until we are woken up to process commands. 5018 5017 */ 5019 { 5020 ASMAtomicWriteBool(&pThisR3->fCmdThreadSleeping, true); 5021 bool fSignaled = ASMAtomicXchgBool(&pThisR3->fCmdThreadSignaled, false); 5022 if (!fSignaled) 5023 { 5024 Assert(ASMAtomicReadBool(&pThisR3->fCmdThreadSleeping)); 5025 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT); 5026 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc); 5027 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING)) 5028 break; 5029 Log4Func(("Woken up with rc=%Rrc\n", rc)); 5030 ASMAtomicWriteBool(&pThisR3->fCmdThreadSignaled, false); 5031 } 5032 ASMAtomicWriteBool(&pThisR3->fCmdThreadSleeping, false); 5018 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false); 5019 if (!fSignaled) 5020 { 5021 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT); 5022 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc); 5023 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING)) 5024 break; 5025 Log4Func(("Woken up with rc=%Rrc\n", rc)); 5026 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false); 5033 5027 } 5034 5028 … … 5175 5169 } 5176 5170 5177 PIOMMU CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);5178 IOMMU_LOCK(pDevIns, pThis CC);5171 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 5172 IOMMU_LOCK(pDevIns, pThisR3); 5179 5173 5180 5174 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3; … … 5256 5250 } 5257 5251 5258 IOMMU_UNLOCK(pDevIns, pThis CC);5252 IOMMU_UNLOCK(pDevIns, pThisR3); 5259 5253 5260 5254 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict))); … … 5972 5966 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", uDomainId, uDomainId); 5973 5967 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 5974 PIOMMU CCpThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);5968 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 5975 5969 IOTLBEINFOARG Args; 5976 5970 Args.pIommuR3 = pThisR3; … … 6128 6122 6129 6123 /** 6124 * @callback_method_impl{FNSSMDEVLIVEEXEC} 6125 */ 6126 static DECLCALLBACK(int) iommuAmdR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass) 6127 { 6128 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 6129 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 6130 RT_NOREF(uPass); 6131 LogFlowFunc(("\n")); 6132 6133 /* Save registers that cannot be modified by the guest. */ 6134 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); 6135 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); 6136 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); 6137 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); 6138 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); 6139 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); 6140 6141 return VINF_SSM_DONT_CALL_AGAIN; 6142 } 6143 6144 6145 /** 6130 6146 * @callback_method_impl{FNSSMDEVSAVEEXEC} 6131 6147 */ 6132 6148 static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 6133 6149 { 6134 /** @todo IOMMU: Save state. */6135 RT_NOREF2(pDevIns, pSSM);6150 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 6151 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 6136 6152 LogFlowFunc(("\n")); 6153 6154 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64); 6155 6156 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs); 6157 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs); 6158 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++) 6159 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64); 6160 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64); 6161 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64); 6162 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64); 6163 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64); 6164 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64); 6165 #if 0 6166 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done in liveExec */ 6167 #endif 6168 6169 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64); 6170 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64); 6171 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo); 6172 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64); 6173 6174 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64); 6175 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64); 6176 6177 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64); 6178 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64); 6179 6180 #if 0 6181 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done in liveExec */ 6182 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done in liveExec */ 6183 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done in liveExec */ 6184 #endif 6185 6186 #if 0 6187 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done in liveExec */ 6188 #endif 6189 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32); 6190 6191 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64); 6192 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64); 6193 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64); 6194 6195 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers); 6196 pHlp->pfnSSMPutU8(pSSM, cMarcApers); 6197 for (size_t i = 0; i < cMarcApers; i++) 6198 { 6199 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64); 6200 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64); 6201 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64); 6202 } 6203 6204 #if 0 6205 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done in liveExec */ 6206 #endif 6207 6208 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64); 6209 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64); 6210 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64); 6211 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64); 6212 6213 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64); 6214 6215 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64); 6216 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64); 6217 6218 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64); 6219 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64); 6220 6221 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64); 6222 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64); 6223 6224 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64); 6225 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64); 6226 6227 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64); 6228 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64); 6229 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64); 6230 6231 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); 6232 } 6233 6234 6235 /** 6236 * @callback_method_impl{FNSSMDEVLOADEXEC} 6237 */ 6238 static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 6239 { 6240 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 6241 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 6242 LogFlowFunc(("\n")); 6243 6244 /* Validate. */ 6245 if (uPass != SSM_PASS_FINAL) 6246 return VINF_SUCCESS; 6247 if (uVersion != IOMMU_SAVED_STATE_VERSION) 6248 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION; 6249 int const rcDataError = VERR_SSM_UNEXPECTED_DATA; 6250 6251 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); 6252 AssertRCReturn(rc, rc); 6253 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3, 6254 ("ExtFeat invalid %#RX64\n", pThis->ExtFeat.u64), rcDataError); 6255 6256 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); 6257 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); 6258 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); 6259 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); 6260 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); 6261 6262 /* Device table base address registers. */ 6263 uint8_t cDevTabBaseAddrs; 6264 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs); 6265 AssertRCReturn(rc, rc); 6266 AssertLogRelMsgReturn(cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs), 6267 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcDataError); 6268 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++) 6269 { 6270 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64); 6271 AssertRCReturn(rc, rc); 6272 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK; 6273 AssertLogRelMsgReturn(pThis->aDevTabBaseAddrs[i].n.u9Size <= g_auDevTabSegMaxSizes[0], 6274 ("Device table segment size invalid %#x\n", pThis->aDevTabBaseAddrs[i].n.u9Size), rcDataError); 6275 } 6276 6277 /* Command buffer base address register. */ 6278 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64); 6279 AssertRCReturn(rc, rc); 6280 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK; 6281 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, 6282 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcDataError); 6283 6284 /* Event log base address register. */ 6285 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64); 6286 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64); 6287 AssertRCReturn(rc, rc); 6288 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK; 6289 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8, 6290 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcDataError); 6291 6292 /* Control register. */ 6293 rc = pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64); 6294 AssertRCReturn(rc, rc); 6295 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK; 6296 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup, 6297 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcDataError); 6298 6299 /** @todo The rest. */ 6137 6300 return VERR_NOT_IMPLEMENTED; 6138 } 6139 6140 6141 /** 6142 * @callback_method_impl{FNSSMDEVLOADEXEC} 6143 */ 6144 static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 6145 { 6146 /** @todo IOMMU: Load state. */ 6147 RT_NOREF4(pDevIns, pSSM, uVersion, uPass); 6148 LogFlowFunc(("\n")); 6149 return VERR_NOT_IMPLEMENTED; 6301 #if 0 6302 pThis->ExclRangeBaseAddr.u64 6303 pThis->ExclRangeLimit.u64 6304 #if 0 6305 pThis->ExtFeat.u64; /* read-only, done in liveExec */ 6306 #endif 6307 6308 pThis->PprLogBaseAddr.u64); 6309 pThis->HwEvtHi.u64); 6310 pThis->HwEvtLo); 6311 pThis->HwEvtStatus.u64); 6312 6313 pThis->GALogBaseAddr.u64); 6314 pThis->GALogTailAddr.u64); 6315 6316 pThis->PprLogBBaseAddr.u64); 6317 pThis->EvtLogBBaseAddr.u64); 6318 6319 #if 0 6320 pThis->DevSpecificFeat.u64); /* read-only, done in liveExec */ 6321 pThis->DevSpecificCtrl.u64); /* read-only, done in liveExec */ 6322 pThis->DevSpecificStatus.u64); /* read-only, done in liveExec */ 6323 #endif 6324 6325 #if 0 6326 pThis->MiscInfo.u64); /* read-only, done in liveExec */ 6327 #endif 6328 pThis->PerfOptCtrl.u32); 6329 6330 pThis->XtGenIntrCtrl.u64); 6331 pThis->XtPprIntrCtrl.u64); 6332 pThis->XtGALogIntrCtrl.u64); 6333 6334 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers); 6335 pHlp->pfnSSMPutU8(pSSM, cMarcApers); 6336 for (size_t i = 0; i < cMarcApers; i++) 6337 { 6338 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64); 6339 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64); 6340 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64); 6341 } 6342 6343 #if 0 6344 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done in liveExec */ 6345 #endif 6346 6347 pThis->CmdBufHeadPtr.u64); 6348 pThis->CmdBufTailPtr.u64); 6349 pThis->EvtLogHeadPtr.u64); 6350 pThis->EvtLogTailPtr.u64); 6351 6352 pThis->Status.u64); 6353 6354 pThis->PprLogHeadPtr.u64); 6355 pThis->PprLogTailPtr.u64); 6356 6357 pThis->GALogHeadPtr.u64); 6358 pThis->GALogTailPtr.u64); 6359 6360 pThis->PprLogBHeadPtr.u64); 6361 pThis->PprLogBTailPtr.u64); 6362 6363 pThis->EvtLogBHeadPtr.u64); 6364 pThis->EvtLogBTailPtr.u64); 6365 6366 pThis->PprLogAutoResp.u64); 6367 pThis->PprLogOverflowEarly.u64); 6368 pThis->PprLogBOverflowEarly.u64); 6369 6370 return VINF_SUCCESS; 6371 #endif 6150 6372 } 6151 6373 … … 6163 6385 */ 6164 6386 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 6165 PIOMMU CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);6387 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 6166 6388 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; 6167 6389 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); 6168 6169 IOMMU_LOCK_NORET(pDevIns, pThisCC);6170 6171 6390 LogFlowFunc(("\n")); 6172 6391 6173 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs)); 6392 IOMMU_LOCK_NORET(pDevIns, pThisR3); 6393 6394 RT_ZERO(pThis->aDevTabBaseAddrs); 6174 6395 6175 6396 pThis->CmdBufBaseAddr.u64 = 0; … … 6209 6430 pThis->XtGALogIntrCtrl.u64 = 0; 6210 6431 6211 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));6432 RT_ZERO(pThis->aMarcApers); 6212 6433 6213 6434 pThis->CmdBufHeadPtr.u64 = 0; … … 6240 6461 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); 6241 6462 6242 IOMMU_UNLOCK(pDevIns, pThis CC);6463 IOMMU_UNLOCK(pDevIns, pThisR3); 6243 6464 6244 6465 #ifdef IOMMU_WITH_DTE_CACHE … … 6261 6482 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); 6262 6483 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 6263 PIOMMU CC pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);6484 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 6264 6485 LogFlowFunc(("\n")); 6265 6486 … … 6297 6518 6298 6519 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 6299 PIOMMU CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);6520 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3); 6300 6521 pThis->u32Magic = IOMMU_MAGIC; 6301 pThis CC->pDevInsR3 = pDevIns;6522 pThisR3->pDevInsR3 = pDevIns; 6302 6523 6303 6524 LogFlowFunc(("iInstance=%d\n", iInstance)); … … 6313 6534 IommuReg.pfnMsiRemap = iommuAmdMsiRemap; 6314 6535 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION; 6315 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThis CC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);6536 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu); 6316 6537 if (RT_FAILURE(rc)) 6317 6538 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device")); 6318 if (pThis CC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)6539 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION) 6319 6540 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS, 6320 6541 N_("IOMMU helper version mismatch; got %#x expected %#x"), 6321 pThis CC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);6322 if (pThis CC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)6542 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION); 6543 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION) 6323 6544 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS, 6324 6545 N_("IOMMU helper end-version mismatch; got %#x expected %#x"), 6325 pThis CC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);6546 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION); 6326 6547 6327 6548 /* … … 6451 6672 * Register saved state. 6452 6673 */ 6453 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL, 6454 NULL, NULL, NULL, 6455 NULL, iommuAmdR3SaveExec, NULL, 6456 NULL, iommuAmdR3LoadExec, NULL); 6674 rc = PDMDevHlpSSMRegister3(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), iommuAmdR3LiveExec, iommuAmdR3SaveExec, 6675 iommuAmdR3LoadExec); 6457 6676 AssertLogRelRCReturn(rc, rc); 6458 6677 … … 6536 6755 RT_ZERO(szDevIommu); 6537 6756 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance); 6538 rc = PDMDevHlpThreadCreate(pDevIns, &pThis CC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,6757 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp, 6539 6758 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu); 6540 6759 AssertLogRelRCReturn(rc, rc); … … 6563 6782 */ 6564 6783 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX; 6565 pThis CC->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);6566 if (!pThis CC->paIotlbes)6784 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes); 6785 if (!pThisR3->paIotlbes) 6567 6786 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS, 6568 6787 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes); 6569 RTListInit(&pThis CC->LstLruIotlbe);6788 RTListInit(&pThisR3->LstLruIotlbe); 6570 6789 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes)); 6571 6790 #endif … … 6614 6833 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0; 6615 6834 6616 pThis->RsvdReg = 0;6617 6618 6835 pThis->DevSpecificFeat.u64 = 0; 6619 6836 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION; … … 6629 6846 6630 6847 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1); 6848 6849 pThis->RsvdReg = 0; 6631 6850 6632 6851 /*
Note:
See TracChangeset
for help on using the changeset viewer.