Changeset 88192 in vbox for trunk/include/VBox/iommu-intel.h
- Timestamp:
- Mar 18, 2021 12:29:30 PM (4 years ago)
- File:
-
- 1 edited
-
trunk/include/VBox/iommu-intel.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/iommu-intel.h
r88174 r88192 39 39 * @{ 40 40 */ 41 #define VTD_MMIO_OFF_VERSION 0x000 /**< Version. */ 42 #define VTD_MMIO_OFF_CAP 0x008 /**< Capability. */ 43 #define VTD_MMIO_OFF_EXT_CAP 0x010 /**< Extended Capability. */ 44 #define VTD_MMIO_OFF_GLOBAL_CMD 0x018 /**< Global Command. */ 45 #define VTD_MMIO_OFF_GLOBAL_STATUS 0x01c /**< Global Status. */ 46 #define VTD_MMIO_OFF_ROOT_TBL_ADDR 0x020 /**< Root Table Address. */ 47 #define VTD_MMIO_OFF_CTX_CMD 0x028 /**< Context Command. */ 48 49 #define VTD_MMIO_OFF_FAULT_STATUS 0x034 /**< Fault Status.*/ 50 #define VTD_MMIO_OFF_FAULT_EVT_CTRL 0x038 /**< Fault Event Control.*/ 51 #define VTD_MMIO_OFF_FAULT_EVT_DATA 0x03c /**< Fault Event Data. */ 52 #define VTD_MMIO_OFF_FAULT_EVT_ADDR 0x040 /**< Fault Event Address. */ 53 #define VTD_MMIO_OFF_FAULT_EVT_UP_ADDR 0x044 /**< Fault Event Upper Address. */ 54 55 #define VTD_MMIO_OFF_ADV_FAULT_LOG 0x058 /**< Advance Fault Log. */ 56 57 #define VTD_MMIO_OFF_PROT_MEM_EN 0x064 /**< Protected Memory Enable (PMEN). */ 58 #define VTD_MMIO_OFF_PROT_LO_MEM_BASE 0x064 /**< Protected Low Memory Base. */ 59 #define VTD_MMIO_OFF_PROT_LO_MEM_LIMIT 0x068 /**< Protected Low Memory Limit. */ 60 #define VTD_MMIO_OFF_PROT_HI_MEM_BASE 0x070 /**< Protected High Memory Base. */ 61 #define VTD_MMIO_OFF_PROT_HI_MEM_LIMIT 0x078 /**< Protected High Memory Limit. */ 62 63 #define VTD_MMIO_OFF_INV_QUEUE_HEAD 0x080 /**< Invalidation Queue Head. */ 64 #define VTD_MMIO_OFF_INV_QUEUE_TAIL 0x088 /**< Invalidation Queue Tail. */ 65 #define VTD_MMIO_OFF_INV_QUEUE_ADDR 0x090 /**< Invalidation Queue Address. */ 66 #define VTD_MMIO_OFF_INV_COMP_STATUS 0x09c /**< Invalidation Completion Status. */ 67 #define VTD_MMIO_OFF_INV_COMP_EVT_CTRL 0x0a0 /**< Invalidation Completion Event Control. */ 68 #define VTD_MMIO_OFF_INV_COMP_EVT_DATA 0x0a4 /**< Invalidation Completion Event Data. */ 69 #define VTD_MMIO_OFF_INV_COMP_EVT_ADDR 0x0a8 /**< Invalidation Completion Event Address. */ 70 #define VTD_MMIO_OFF_INV_COMP_EVT_UP_ADDR 0x0ac /**< Invalidation Completion Event Upper Address. */ 71 #define VTD_MMIO_OFF_INV_QUEUE_ERR_RECORD 0x0b0 /**< Invalidation Completion Queue Error Record. */ 72 73 #define VTD_MMIO_OFF_IRT_ADDR 0x0b8 /**< Interrupt Remapping Table Address. */ 74 75 #define VTD_MMIO_OFF_PAGE_REQ_QUEUE_HEAD 0x0c0 /**< Page Request Queue Head. */ 76 #define VTD_MMIO_OFF_PAGE_REQ_QUEUE_TAIL 0x0c8 /**< Page Request Queue Tail. */ 77 #define VTD_MMIO_OFF_PAGE_REQ_STATUS 0x0dc /**< Page Request Status. */ 78 #define VTD_MMIO_OFF_PAGE_REQ_EVT_CTRL 0x0e0 /**< Page Request Event Control. */ 79 #define VTD_MMIO_OFF_PAGE_REQ_EVT_DATA 0x0e4 /**< Page Request Event Data. */ 80 #define VTD_MMIO_OFF_PAGE_REQ_EVT_ADDR 0x0e8 /**< Page Request Event Address. */ 81 #define VTD_MMIO_OFF_PAGE_REQ_EVT_UP_ADDR 0x0ec /**< Page Request Event Upper Address. */ 82 83 #define VTD_MMIO_OFF_MTRR_CAP 0x100 /**< MTRR Capabliity. */ 84 #define VTD_MMIO_OFF_MTRR_DEF_TYPE 0x108 /**< MTRR Default Type. */ 85 86 #define VTD_MMIO_OFF_MTRR_FIXED_00000 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */ 87 #define VTD_MMIO_OFF_MTRR_FIXED_80000 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */ 88 #define VTD_MMIO_OFF_MTRR_FIXED_A0000 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */ 89 #define VTD_MMIO_OFF_MTRR_FIXED_C0000 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */ 90 #define VTD_MMIO_OFF_MTRR_FIXED_C8000 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */ 91 #define VTD_MMIO_OFF_MTRR_FIXED_D0000 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */ 92 #define VTD_MMIO_OFF_MTRR_FIXED_D8000 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */ 93 #define VTD_MMIO_OFF_MTRR_FIXED_E0000 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */ 94 #define VTD_MMIO_OFF_MTRR_FIXED_E8000 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */ 95 #define VTD_MMIO_OFF_MTRR_FIXED_F0000 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */ 96 #define VTD_MMIO_OFF_MTRR_FIXED_F8000 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */ 97 98 #define VTD_MMIO_OFF_MTRR_VAR_BASE_0 0x180 /**< Variable-range MTRR Base 0. */ 99 #define VTD_MMIO_OFF_MTRR_VAR_MASK_0 0x188 /**< Variable-range MTRR Mask 0. */ 100 #define VTD_MMIO_OFF_MTRR_VAR_BASE_1 0x190 /**< Variable-range MTRR Base 1. */ 101 #define VTD_MMIO_OFF_MTRR_VAR_MASK_1 0x198 /**< Variable-range MTRR Mask 1. */ 102 #define VTD_MMIO_OFF_MTRR_VAR_BASE_2 0x1a0 /**< Variable-range MTRR Base 2. */ 103 #define VTD_MMIO_OFF_MTRR_VAR_MASK_2 0x1a8 /**< Variable-range MTRR Mask 2. */ 104 #define VTD_MMIO_OFF_MTRR_VAR_BASE_3 0x1b0 /**< Variable-range MTRR Base 3. */ 105 #define VTD_MMIO_OFF_MTRR_VAR_MASK_3 0x1b8 /**< Variable-range MTRR Mask 3. */ 106 #define VTD_MMIO_OFF_MTRR_VAR_BASE_4 0x1c0 /**< Variable-range MTRR Base 4. */ 107 #define VTD_MMIO_OFF_MTRR_VAR_MASK_4 0x1c8 /**< Variable-range MTRR Mask 4. */ 108 #define VTD_MMIO_OFF_MTRR_VAR_BASE_5 0x1d0 /**< Variable-range MTRR Base 5. */ 109 #define VTD_MMIO_OFF_MTRR_VAR_MASK_5 0x1d8 /**< Variable-range MTRR Mask 5. */ 110 #define VTD_MMIO_OFF_MTRR_VAR_BASE_6 0x1e0 /**< Variable-range MTRR Base 6. */ 111 #define VTD_MMIO_OFF_MTRR_VAR_MASK_6 0x1e8 /**< Variable-range MTRR Mask 6. */ 112 #define VTD_MMIO_OFF_MTRR_VAR_BASE_7 0x1f0 /**< Variable-range MTRR Base 7. */ 113 #define VTD_MMIO_OFF_MTRR_VAR_MASK_7 0x1f8 /**< Variable-range MTRR Mask 7. */ 114 #define VTD_MMIO_OFF_MTRR_VAR_BASE_8 0x200 /**< Variable-range MTRR Base 8. */ 115 #define VTD_MMIO_OFF_MTRR_VAR_MASK_8 0x208 /**< Variable-range MTRR Mask 8. */ 116 #define VTD_MMIO_OFF_MTRR_VAR_BASE_9 0x210 /**< Variable-range MTRR Base 9. */ 117 #define VTD_MMIO_OFF_MTRR_VAR_MASK_9 0x218 /**< Variable-range MTRR Mask 9. */ 118 119 #define VTD_MMIO_OFF_VIRT_CMD_CAP 0xe00 /**< Virtual Command Capability. */ 120 #define VTD_MMIO_OFF_VIRT_CMD 0xe10 /**< Virtual Command. */ 121 #define VTD_MMIO_OFF_VIRT_CMD_RESP 0xe20 /**< Virtual Command Response. */ 41 #define VTD_MMIO_GROUP_0_OFF_FIRST 0x000 42 #define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */ 43 #define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */ 44 #define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */ 45 #define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */ 46 #define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */ 47 #define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */ 48 #define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */ 49 50 #define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/ 51 #define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/ 52 #define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */ 53 #define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */ 54 #define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */ 55 56 #define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */ 57 58 #define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */ 59 #define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */ 60 #define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */ 61 #define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */ 62 #define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */ 63 64 #define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */ 65 #define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */ 66 #define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */ 67 #define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */ 68 #define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */ 69 #define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */ 70 #define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */ 71 #define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */ 72 #define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */ 73 74 #define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */ 75 76 #define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */ 77 #define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */ 78 #define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */ 79 #define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */ 80 #define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */ 81 #define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */ 82 #define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */ 83 #define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */ 84 85 #define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */ 86 #define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */ 87 88 #define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */ 89 #define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */ 90 #define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */ 91 #define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */ 92 #define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */ 93 #define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */ 94 #define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */ 95 #define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */ 96 #define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */ 97 #define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */ 98 #define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */ 99 100 #define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */ 101 #define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */ 102 #define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */ 103 #define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */ 104 #define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */ 105 #define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */ 106 #define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */ 107 #define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */ 108 #define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */ 109 #define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */ 110 #define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */ 111 #define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */ 112 #define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */ 113 #define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */ 114 #define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */ 115 #define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */ 116 #define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */ 117 #define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */ 118 #define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */ 119 #define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */ 120 #define VTD_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 121 #define VTD_MMIO_GROUP_0_OFF_END (VTD_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */) 122 123 #define VTD_MMIO_GROUP_1_OFF_FIRST 0x000 124 #define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */ 125 #define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */ 126 #define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */ 127 #define VTD_MMIO_GROUP_1_OFF_LAST VTD_MMIO_OFF_VCRSP_REG 128 #define VTD_MMIO_GROUP_1_OFF_END (VTD_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof VCRSP_REG */) 129 130 #define VTD_MMIO_GROUP_0_SIZE (VTD_MMIO_GROUP_0_OFF_END - VTD_MMIO_GROUP_0_OFF_FIRST) /*bytes*/ 131 #define VTD_MMIO_GROUP_1_SIZE (VTD_MMIO_GROUP_1_OFF_END - VTD_MMIO_GROUP_1_OFF_FIRST) /*bytes*/ 122 132 /** @} */ 123 133
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