Index: /trunk/src/recompiler/target-i386/translate.c
===================================================================
--- /trunk/src/recompiler/target-i386/translate.c	(revision 8825)
+++ /trunk/src/recompiler/target-i386/translate.c	(revision 8826)
@@ -1,5 +1,5 @@
 /*
  *  i386 translation
- * 
+ *
  *  Copyright (c) 2003 Fabrice Bellard
  *
@@ -145,11 +145,11 @@
 /* i386 arith/logic operations */
 enum {
-    OP_ADDL, 
-    OP_ORL, 
-    OP_ADCL, 
+    OP_ADDL,
+    OP_ORL,
+    OP_ADCL,
     OP_SBBL,
-    OP_ANDL, 
-    OP_SUBL, 
-    OP_XORL, 
+    OP_ANDL,
+    OP_SUBL,
+    OP_XORL,
     OP_CMPL,
 };
@@ -157,10 +157,10 @@
 /* i386 shift ops */
 enum {
-    OP_ROL, 
-    OP_ROR, 
-    OP_RCL, 
-    OP_RCR, 
-    OP_SHL, 
-    OP_SHR, 
+    OP_ROL,
+    OP_ROR,
+    OP_RCL,
+    OP_RCR,
+    OP_SHL,
+    OP_SHR,
     OP_SHL1, /* undocumented */
     OP_SAR = 7,
@@ -180,5 +180,5 @@
     OT_BYTE = 0,
     OT_WORD,
-    OT_LONG, 
+    OT_LONG,
     OT_QUAD,
 };
@@ -369,5 +369,5 @@
 };
 
-static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] = 
+static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
 {
     [OT_BYTE] = {
@@ -940,5 +940,5 @@
     X86_64_ONLY(gen_op_jnz_ecxq),
 };
-    
+
 static GenOpFunc1 *gen_op_jz_ecx[3] = {
     gen_op_jz_ecxw,
@@ -1028,5 +1028,5 @@
         gen_op_addq_ESI_T0();
         gen_op_addq_EDI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1071,5 +1071,5 @@
     if (s->aflag == 2) {
         gen_op_addq_EDI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1089,5 +1089,5 @@
     if (s->aflag == 2) {
         gen_op_addq_ESI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1108,5 +1108,5 @@
     if (s->aflag == 2) {
         gen_op_addq_EDI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1129,5 +1129,5 @@
         gen_op_addq_ESI_T0();
         gen_op_addq_EDI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1151,5 +1151,5 @@
     if (s->aflag == 2) {
         gen_op_addq_EDI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1169,5 +1169,5 @@
     if (s->aflag == 2) {
         gen_op_addq_ESI_T0();
-    } else 
+    } else
 #endif
     if (s->aflag) {
@@ -1380,5 +1380,5 @@
 {
     GenOpFunc *gen_update_cc;
-    
+
     if (d != OR_TMP0) {
         gen_op_mov_TN_reg[ot][0][d]();
@@ -1470,5 +1470,5 @@
     if (s1->cc_op != CC_OP_DYNAMIC)
         gen_op_set_cc_op(s1->cc_op);
-    
+
     if (d != OR_TMP0)
         gen_op_shift_T0_T1_cc[ot][op]();
@@ -1510,5 +1510,5 @@
         index = 0;
         scale = 0;
-        
+
         if (base == 4) {
             havesib = 1;
@@ -1542,5 +1542,5 @@
             break;
         }
-        
+
         if (base >= 0) {
             /* for correct popl handling with esp */
@@ -1556,5 +1556,5 @@
                         gen_op_addq_A0_im64(disp >> 32, disp);
                 }
-            } else 
+            } else
 #endif
             {
@@ -1570,5 +1570,5 @@
                 else
                     gen_op_movq_A0_im64(disp >> 32, disp);
-            } else 
+            } else
 #endif
             {
@@ -1581,5 +1581,5 @@
             if (s->aflag == 2) {
                 gen_op_addq_A0_reg_sN[scale][index]();
-            } else 
+            } else
 #endif
             {
@@ -1597,5 +1597,5 @@
             if (s->aflag == 2) {
                 gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
-            } else 
+            } else
 #endif
             {
@@ -1689,10 +1689,10 @@
 
         base = rm;
-        
+
         if (base == 4) {
             code = ldub_code(s->pc++);
             base = (code & 7);
         }
-        
+
         switch (mod) {
         case 0:
@@ -1743,5 +1743,5 @@
         if (CODE64(s)) {
             gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
-        } else 
+        } else
 #endif
         {
@@ -1838,5 +1838,5 @@
 }
 
-static inline void gen_jcc(DisasContext *s, int b, 
+static inline void gen_jcc(DisasContext *s, int b,
                            target_ulong val, target_ulong next_eip)
 {
@@ -1849,5 +1849,5 @@
     inv = b & 1;
     jcc_op = (b >> 1) & 7;
-    
+
     if (s->jmp_opt) {
 #ifdef VBOX
@@ -1862,5 +1862,5 @@
             func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
             break;
-            
+
             /* some jumps are easy to compute */
         case CC_OP_ADDB:
@@ -1929,5 +1929,5 @@
             func = gen_op_jnz_T0_label;
         }
-    
+
         if (inv) {
             tmp = val;
@@ -1987,5 +1987,5 @@
             goto slow_jcc;
         break;
-        
+
         /* some jumps are easy to compute */
     case CC_OP_ADDB:
@@ -2066,5 +2066,5 @@
         if (addend == 8)
             gen_op_addq_ESP_8();
-        else 
+        else
             gen_op_addq_ESP_im(addend);
     } else
@@ -2075,5 +2075,5 @@
         else if (addend == 4)
             gen_op_addl_ESP_4();
-        else 
+        else
             gen_op_addl_ESP_im(addend);
     } else {
@@ -2101,5 +2101,5 @@
         }
         gen_op_movq_ESP_A0();
-    } else 
+    } else
 #endif
     {
@@ -2142,5 +2142,5 @@
         }
         gen_op_movq_ESP_A0();
-    } else 
+    } else
 #endif
     {
@@ -2159,5 +2159,5 @@
         }
         gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
-        
+
         if (s->ss32 && !s->addseg)
             gen_op_movl_ESP_A0();
@@ -2174,5 +2174,5 @@
         gen_op_movq_A0_reg[R_ESP]();
         gen_op_ld_T0_A0[(s->dflag ? OT_QUAD : OT_WORD) + s->mem_index]();
-    } else 
+    } else
 #endif
     {
@@ -2261,5 +2261,5 @@
         ot = s->dflag ? OT_QUAD : OT_WORD;
         opsize = 1 << ot;
-        
+
         gen_op_movl_A0_ESP();
         gen_op_addq_A0_im(-opsize);
@@ -2275,10 +2275,10 @@
         gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
         gen_op_mov_reg_T1[OT_QUAD][R_ESP]();
-    } else 
+    } else
 #endif
     {
         ot = s->dflag + OT_WORD;
         opsize = 2 << s->dflag;
-        
+
         gen_op_movl_A0_ESP();
         gen_op_addl_A0_im(-opsize);
@@ -2311,5 +2311,5 @@
 /* an interrupt is different from an exception because of the
    priviledge checks */
-static void gen_interrupt(DisasContext *s, int intno, 
+static void gen_interrupt(DisasContext *s, int intno,
                           target_ulong cur_eip, target_ulong next_eip)
 {
@@ -2377,5 +2377,5 @@
 static void gen_movtl_T0_im(target_ulong val)
 {
-#ifdef TARGET_X86_64    
+#ifdef TARGET_X86_64
     if ((int32_t)val == val) {
         gen_op_movl_T0_im(val);
@@ -2390,5 +2390,5 @@
 static void gen_movtl_T1_im(target_ulong val)
 {
-#ifdef TARGET_X86_64    
+#ifdef TARGET_X86_64
     if ((int32_t)val == val) {
         gen_op_movl_T1_im(val);
@@ -2478,5 +2478,5 @@
     [0x58] = SSE_FOP(add),
     [0x59] = SSE_FOP(mul),
-    [0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps, 
+    [0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
                gen_op_cvtss2sd, gen_op_cvtsd2ss },
     [0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
@@ -2506,7 +2506,7 @@
     [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
     [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
-    [0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx, 
-               (GenOpFunc2 *)gen_op_pshufd_xmm, 
-               (GenOpFunc2 *)gen_op_pshufhw_xmm, 
+    [0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
+               (GenOpFunc2 *)gen_op_pshufd_xmm,
+               (GenOpFunc2 *)gen_op_pshufhw_xmm,
                (GenOpFunc2 *)gen_op_pshuflw_xmm },
     [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
@@ -2590,5 +2590,5 @@
     X86_64_ONLY(gen_op_cvtsq2ss),
     X86_64_ONLY(gen_op_cvtsq2sd),
-    
+
     gen_op_cvttss2si,
     gen_op_cvttsd2si,
@@ -2601,5 +2601,5 @@
     X86_64_ONLY(gen_op_cvtsd2sq),
 };
-    
+
 static GenOpFunc2 *sse_op_table4[8][4] = {
     SSE_FOP(cmpeq),
@@ -2612,5 +2612,5 @@
     SSE_FOP(cmpord),
 };
-    
+
 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
 {
@@ -2621,14 +2621,14 @@
 
     b &= 0xff;
-    if (s->prefix & PREFIX_DATA) 
+    if (s->prefix & PREFIX_DATA)
         b1 = 1;
-    else if (s->prefix & PREFIX_REPZ) 
+    else if (s->prefix & PREFIX_REPZ)
         b1 = 2;
-    else if (s->prefix & PREFIX_REPNZ) 
+    else if (s->prefix & PREFIX_REPNZ)
         b1 = 3;
     else
         b1 = 0;
     sse_op2 = sse_op_table1[b][b1];
-    if (!sse_op2) 
+    if (!sse_op2)
         goto illegal_op;
     if (b <= 0x5f || b == 0xc6 || b == 0xc2) {
@@ -2674,5 +2674,5 @@
         switch(b) {
         case 0x0e7: /* movntq */
-            if (mod == 3) 
+            if (mod == 3)
                 goto illegal_op;
             gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
@@ -2693,5 +2693,5 @@
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
                 gen_op_movq_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
-            } else 
+            } else
 #endif
             {
@@ -2705,5 +2705,5 @@
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
                 gen_op_movq_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
-            } else 
+            } else
 #endif
             {
@@ -2838,5 +2838,5 @@
                 gen_op_movq_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
-            } else 
+            } else
 #endif
             {
@@ -2850,5 +2850,5 @@
                 gen_op_movq_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
-            } else 
+            } else
 #endif
             {
@@ -3050,10 +3050,10 @@
                 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
             }
-            sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + 
+            sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
                           (b & 1) * 4](op2_offset);
             gen_op_mov_reg_T0[ot][reg]();
             break;
         case 0xc4: /* pinsrw */
-        case 0x1c4: 
+        case 0x1c4:
             s->rip_offset = 1;
             gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
@@ -3068,5 +3068,5 @@
             break;
         case 0xc5: /* pextrw */
-        case 0x1c5: 
+        case 0x1c5:
             if (mod != 3)
                 goto illegal_op;
@@ -3130,10 +3130,10 @@
         case 0xf7:
             /* maskmov : we must prepare A0 */
-            if (mod != 3) 
+            if (mod != 3)
                 goto illegal_op;
 #ifdef TARGET_X86_64
             if (s->aflag == 2) {
                 gen_op_movq_A0_reg[R_EDI]();
-            } else 
+            } else
 #endif
             {
@@ -3211,4 +3211,146 @@
 }
 
+#ifdef VBOX
+/* Checks if it's an invalid lock sequence. Only a few instructions
+   can be used together with the lock prefix and of those only the
+   form that write a memory operand. So, this is kind of annoying
+   work to do...
+   The AMD manual lists the following instructions.
+        ADC
+        ADD
+        AND
+        BTC
+        BTR
+        BTS
+        CMPXCHG
+        CMPXCHG8B
+        CMPXCHG16B
+        DEC
+        INC
+        NEG
+        NOT
+        OR
+        SBB
+        SUB
+        XADD
+        XCHG
+        XOR */
+static bool is_invalid_lock_sequence(DisasContext *s, target_ulong pc_start, int b)
+{
+#if 0 /** @todo test this properly! */
+    target_ulong pc = s->pc;
+    int modrm, mod, op;
+
+    /* X={8,16,32,64}  Y={16,32,64} */
+    switch (b)
+    {
+        /* /2: ADC reg/memX, immX */
+        /* /0: ADD reg/memX, immX */
+        /* /4: AND reg/memX, immX */
+        /* /1: OR  reg/memX, immX */
+        /* /3: SBB reg/memX, immX */
+        /* /5: SUB reg/memX, immX */
+        /* /6: XOR reg/memX, immX */
+        case 0x80:
+        case 0x81:
+        case 0x83:
+            modrm = ldub_code(pc++);
+            op = (modrm >> 3) & 7;
+            if (op == 7) /* /7: CMP */
+                break;
+            mod = (modrm >> 6) & 3;
+            if (mod == 3) /* register destination */
+                break;
+            return false;
+
+        case 0x10: /* /r: ADC reg/mem8, reg8 */
+        case 0x11: /* /r: ADC reg/memX, regY */
+        case 0x00: /* /r: ADD reg/mem8, reg8 */
+        case 0x01: /* /r: ADD reg/memX, regY */
+        case 0x20: /* /r: AND reg/mem8, reg8 */
+        case 0x21: /* /r: AND reg/memY, regY */
+        case 0x08: /* /r: OR  reg/mem8, reg8 */
+        case 0x09: /* /r: OR  reg/memY, regY */
+        case 0x18: /* /r: SBB reg/mem8, reg8 */
+        case 0x19: /* /r: SBB reg/memY, regY */
+        case 0x28: /* /r: SUB reg/mem8, reg8 */
+        case 0x29: /* /r: SUB reg/memY, regY */
+        case 0x86: /* /r: XCHG reg/mem8, reg8 or XCHG reg8, reg/mem8 */
+        case 0x87: /* /r: XCHG reg/memY, regY or XCHG regY, reg/memY */
+        case 0x30: /* /r: XOR reg/mem8, reg8 */
+        case 0x31: /* /r: XOR reg/memY, regY */
+            modrm = ldub_code(pc++);
+            mod = (modrm >> 6) & 3;
+            if (mod == 3) /* register destination */
+                break;
+            return false;
+
+        /* /1: DEC reg/memX */
+        /* /0: INC reg/memX */
+        case 0xfe:
+        case 0xff:
+            modrm = ldub_code(pc++);
+            mod = (modrm >> 6) & 3;
+            if (mod == 3) /* register destination */
+                break;
+            return false;
+
+        /* /3: NEG reg/memX */
+        /* /2: NOT reg/memX */
+        case 0xf6:
+        case 0xf7:
+            modrm = ldub_code(pc++);
+            mod = (modrm >> 6) & 3;
+            if (mod == 3) /* register destination */
+                break;
+            return false;
+
+        case 0x0f:
+            b = ldub_code(pc++);
+            switch (b)
+            {
+                /* /7: BTC reg/memY, imm8 */
+                /* /6: BTR reg/memY, imm8 */
+                /* /5: BTS reg/memY, imm8 */
+                case 0xba:
+                    modrm = ldub_code(pc++);
+                    op = (modrm >> 3) & 7;
+                    if (op < 5)
+                        break;
+                    mod = (modrm >> 6) & 3;
+                    if (mod == 3) /* register destination */
+                        break;
+                    return false;
+
+                case 0xbb: /* /r: BTC reg/memY, regY */
+                case 0xb3: /* /r: BTR reg/memY, regY */
+                case 0xab: /* /r: BTS reg/memY, regY */
+                case 0xb0: /* /r: CMPXCHG reg/mem8, reg8 */
+                case 0xb1: /* /r: CMPXCHG reg/memY, regY */
+                case 0xc0: /* /r: XADD reg/mem8, reg8 */
+                case 0xc1: /* /r: XADD reg/memY, regY */
+                    modrm = ldub_code(pc++);
+                    mod = (modrm >> 6) & 3;
+                    if (mod == 3) /* register destination */
+                        break;
+                    return false;
+
+                /* /1: CMPXCHG8B mem64 or CMPXCHG16B mem128 */
+                case 0xc7:
+                    return false;
+            }
+            break;
+    }
+
+    /* illegal sequence. */
+    Log(("illegal lock sequence %VGv (b=%#x)\n", pc_start, b));
+    s->pc = pc; /* XXX: What's the correct value here? */
+    return true;
+#else
+    return false;
+#endif
+}
+#endif /* VBOX */
+
 
 /* convert one instruction. s->is_jmp is set if the translation must
@@ -3232,5 +3374,5 @@
     s->rex_x = 0;
     s->rex_b = 0;
-    x86_64_hregs = 0; 
+    x86_64_hregs = 0;
 #endif
     s->rip_offset = 0; /* for relative ip address */
@@ -3299,5 +3441,5 @@
         if (!(prefixes & PREFIX_ADR))
             aflag = 2;
-    } else 
+    } else
 #endif
     {
@@ -3348,6 +3490,16 @@
 
     /* lock generation */
+#ifndef VBOX
     if (prefixes & PREFIX_LOCK)
         gen_op_lock();
+#else /* VBOX */
+    if (prefixes & PREFIX_LOCK) {
+        if (is_invalid_lock_sequence(s, pc_start, b)) {
+            gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
+            return s->pc;
+        }
+        gen_op_lock();
+    }
+#endif /* VBOX */
 
     /* now check op code */
@@ -3359,5 +3511,5 @@
         b = ldub_code(s->pc++) | 0x100;
         goto reswitch;
-        
+
         /**************************/
         /* arith & logic */
@@ -3379,5 +3531,5 @@
             else
                 ot = dflag + OT_WORD;
-            
+
             switch(f) {
             case 0: /* OP Ev, Gv */
@@ -3438,10 +3590,10 @@
             else
                 ot = dflag + OT_WORD;
-            
+
             modrm = ldub_code(s->pc++);
             mod = (modrm >> 6) & 3;
             rm = (modrm & 7) | REX_B(s);
             op = (modrm >> 3) & 7;
-            
+
             if (mod != 3) {
                 if (b == 0x83)
@@ -3734,5 +3886,5 @@
 
     case 0x84: /* test Ev, Gv */
-    case 0x85: 
+    case 0x85:
         if ((b & 1) == 0)
             ot = OT_BYTE;
@@ -3744,5 +3896,5 @@
         rm = (modrm & 7) | REX_B(s);
         reg = ((modrm >> 3) & 7) | rex_r;
-        
+
         gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
         gen_op_mov_TN_reg[ot][1][reg]();
@@ -3750,5 +3902,5 @@
         s->cc_op = CC_OP_LOGICB + ot;
         break;
-        
+
     case 0xa8: /* test eAX, Iv */
     case 0xa9:
@@ -3764,5 +3916,5 @@
         s->cc_op = CC_OP_LOGICB + ot;
         break;
-        
+
     case 0x98: /* CWDE/CBW */
 #ifdef TARGET_X86_64
@@ -3881,5 +4033,5 @@
         s->cc_op = CC_OP_EFLAGS;
         break;
-        
+
         /**************************/
         /* push/pop */
@@ -4032,5 +4184,5 @@
         modrm = ldub_code(s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
-        
+
         /* generate a generic store */
         gen_ldst_modrm(s, modrm, ot, reg, 1);
@@ -4057,4 +4209,8 @@
     case 0x8a:
     case 0x8b: /* mov Ev, Gv */
+#ifdef VBOX /* dtrace hot fix */
+        if (prefixes & PREFIX_LOCK)
+            goto illegal_op;
+#endif
         if ((b & 1) == 0)
             ot = OT_BYTE;
@@ -4063,5 +4219,5 @@
         modrm = ldub_code(s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
-        
+
         gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
         gen_op_mov_reg_T0[ot][reg]();
@@ -4115,5 +4271,5 @@
             mod = (modrm >> 6) & 3;
             rm = (modrm & 7) | REX_B(s);
-            
+
             if (mod == 3) {
                 gen_op_mov_TN_reg[ot][0][rm]();
@@ -4161,5 +4317,5 @@
         gen_op_mov_reg_A0[ot - OT_WORD][reg]();
         break;
-        
+
     case 0xa0: /* mov EAX, Ov */
     case 0xa1:
@@ -4181,5 +4337,5 @@
                 else
                     gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
-            } else 
+            } else
 #endif
             {
@@ -4206,5 +4362,5 @@
             gen_op_movq_A0_reg[R_EBX]();
             gen_op_addq_A0_AL();
-        } else 
+        } else
 #endif
         {
@@ -4233,5 +4389,5 @@
             gen_movtl_T0_im(tmp);
             gen_op_mov_reg_T0[OT_QUAD][reg]();
-        } else 
+        } else
 #endif
         {
@@ -4316,5 +4472,5 @@
         }
         break;
-        
+
         /************************/
         /* shifts */
@@ -4329,9 +4485,9 @@
             else
                 ot = dflag + OT_WORD;
-            
+
             modrm = ldub_code(s->pc++);
             mod = (modrm >> 6) & 3;
             op = (modrm >> 3) & 7;
-            
+
             if (mod != 3) {
                 if (shift == 2) {
@@ -4387,5 +4543,5 @@
         rm = (modrm & 7) | REX_B(s);
         reg = ((modrm >> 3) & 7) | rex_r;
-        
+
         if (mod != 3) {
             gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
@@ -4395,5 +4551,5 @@
         }
         gen_op_mov_TN_reg[ot][1][reg]();
-        
+
         if (shift) {
             val = ldub_code(s->pc++);
@@ -4428,5 +4584,5 @@
         /************************/
         /* floats */
-    case 0xd8 ... 0xdf: 
+    case 0xd8 ... 0xdf:
         if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
             /* if CR0.EM or CR0.TS are set, generate an FPU exception */
@@ -4466,5 +4622,5 @@
                         break;
                     }
-                    
+
                     gen_op_fp_arith_ST0_FT0[op1]();
                     if (op1 == 3) {
@@ -4723,5 +4879,5 @@
                 {
                     int op1;
-                    
+
                     op1 = op & 7;
                     if (op >= 0x20) {
@@ -4793,5 +4949,5 @@
             case 0x28: /* ffree sti */
                 gen_op_ffree_STN(opreg);
-                break; 
+                break;
             case 0x2a: /* fst sti */
                 gen_op_fmov_STN_ST0(opreg);
@@ -4893,5 +5049,5 @@
         }
         break;
-        
+
     case 0xaa: /* stosS */
     case 0xab:
@@ -5127,5 +5283,5 @@
         {
             unsigned int selector, offset;
-            
+
             if (CODE64(s))
                 goto illegal_op;
@@ -5133,5 +5289,5 @@
             offset = insn_get(s, ot);
             selector = insn_get(s, OT_WORD);
-            
+
             gen_op_movl_T0_im(selector);
             gen_op_movl_T1_imu(offset);
@@ -5157,5 +5313,5 @@
             offset = insn_get(s, ot);
             selector = insn_get(s, OT_WORD);
-            
+
             gen_op_movl_T0_im(selector);
             gen_op_movl_T1_imu(offset);
@@ -5176,5 +5332,5 @@
             tval = (int32_t)insn_get(s, OT_LONG);
         } else {
-            tval = (int16_t)insn_get(s, OT_WORD); 
+            tval = (int16_t)insn_get(s, OT_WORD);
         }
     do_jcc:
@@ -5206,5 +5362,5 @@
         gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
         break;
-        
+
         /************************/
         /* flags */
@@ -5453,5 +5609,5 @@
         break;
     case 0x9b: /* fwait */
-        if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == 
+        if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
             (HF_MP_MASK | HF_TS_MASK)) {
             gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
@@ -5466,6 +5622,6 @@
 #ifdef VBOX
         if (s->vm86 && s->iopl != 3 && !s->vme) {
-            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); 
-        } else 
+            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+        } else
 #endif
             gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
@@ -5478,5 +5634,5 @@
         if (s->vm86 && s->iopl != 3) {
 #endif
-            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); 
+            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
         } else {
             gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
@@ -5574,5 +5730,5 @@
             gen_op_bswapq_T0();
             gen_op_mov_reg_T0[OT_QUAD][reg]();
-        } else 
+        } else
 #endif
         {
@@ -5604,5 +5760,5 @@
             if (s->dflag == 0)
                 tval &= 0xffff;
-            
+
             l1 = gen_new_label();
             l2 = gen_new_label();
@@ -5804,5 +5960,5 @@
                         gen_op_movq_A0_reg[R_EBX]();
                         gen_op_addq_A0_AL();
-                    } else 
+                    } else
 #endif
                     {
@@ -5889,5 +6045,5 @@
                         gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
                         gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
-                    } else 
+                    } else
 #endif
                     {
@@ -5925,5 +6081,5 @@
             mod = (modrm >> 6) & 3;
             rm = (modrm & 7) | REX_B(s);
-            
+
             if (mod == 3) {
                 gen_op_mov_TN_reg[OT_LONG][0][rm]();
@@ -5941,5 +6097,5 @@
                 gen_op_mov_reg_T0[d_ot][reg]();
             }
-        } else 
+        } else
 #endif
         {
@@ -6039,5 +6195,5 @@
                     gen_eob(s);
                 } else {
-#if !defined(CONFIG_USER_ONLY) 
+#if !defined(CONFIG_USER_ONLY)
                     if (reg == 8)
                         gen_op_movtl_T0_cr8();
@@ -6110,5 +6266,5 @@
         switch(op) {
         case 0: /* fxsave */
-            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || 
+            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
                 (s->flags & HF_EM_MASK))
                 goto illegal_op;
@@ -6121,5 +6277,5 @@
             break;
         case 1: /* fxrstor */
-            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || 
+            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
                 (s->flags & HF_EM_MASK))
                 goto illegal_op;
@@ -6214,5 +6370,5 @@
 
 /* flags read by an operation */
-static uint16_t opc_read_flags[NB_OPS] = { 
+static uint16_t opc_read_flags[NB_OPS] = {
     [INDEX_op_aas] = CC_A,
     [INDEX_op_aaa] = CC_A,
@@ -6221,5 +6377,5 @@
 
     /* subtle: due to the incl/decl implementation, C is used */
-    [INDEX_op_update_inc_cc] = CC_C, 
+    [INDEX_op_update_inc_cc] = CC_C,
 
     [INDEX_op_into] = CC_O,
@@ -6347,5 +6503,5 @@
 
 /* flags written by an operation */
-static uint16_t opc_write_flags[NB_OPS] = { 
+static uint16_t opc_write_flags[NB_OPS] = {
     [INDEX_op_update2_cc] = CC_OSZAPC,
     [INDEX_op_update1_cc] = CC_OSZAPC,
@@ -6353,5 +6509,5 @@
     [INDEX_op_update_neg_cc] = CC_OSZAPC,
     /* subtle: due to the incl/decl implementation, C is used */
-    [INDEX_op_update_inc_cc] = CC_OSZAPC, 
+    [INDEX_op_update_inc_cc] = CC_OSZAPC,
     [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
 
@@ -6498,5 +6654,5 @@
 
 /* simpler form of an operation if no flags need to be generated */
-static uint16_t opc_simpler[NB_OPS] = { 
+static uint16_t opc_simpler[NB_OPS] = {
     [INDEX_op_update2_cc] = INDEX_op_nop,
     [INDEX_op_update1_cc] = INDEX_op_nop,
@@ -6582,5 +6738,5 @@
    information for each intermediate instruction. */
 static inline int gen_intermediate_code_internal(CPUState *env,
-                                                 TranslationBlock *tb, 
+                                                 TranslationBlock *tb,
                                                  int search_pc)
 {
@@ -6591,5 +6747,5 @@
     target_ulong pc_start;
     target_ulong cs_base;
-    
+
     /* generate intermediate code */
     pc_start = tb->pc;
@@ -6686,5 +6842,5 @@
 #ifdef DEBUG
 /*
-        if(cpu_check_code_raw(env, pc_ptr, env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK))) == ERROR_SUCCESS) 
+        if(cpu_check_code_raw(env, pc_ptr, env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK))) == ERROR_SUCCESS)
         {
             //should never happen as the jump to the patch code terminates the translation block
@@ -6693,5 +6849,5 @@
 */
 #endif
-        if (env->state & CPU_EMULATE_SINGLE_INSTR) 
+        if (env->state & CPU_EMULATE_SINGLE_INSTR)
         {
             env->state &= ~CPU_EMULATE_SINGLE_INSTR;
@@ -6707,5 +6863,5 @@
            the flag and abort the translation to give the irqs a
            change to be happen */
-        if (dc->tf || dc->singlestep_enabled || 
+        if (dc->tf || dc->singlestep_enabled ||
             (flags & HF_INHIBIT_IRQ_MASK) ||
             (cflags & CF_SINGLE_INSN)) {
@@ -6730,5 +6886,5 @@
             gen_opc_instr_start[lj++] = 0;
     }
-        
+
 #ifdef DEBUG_DISAS
     if (loglevel & CPU_LOG_TB_CPU) {
