VirtualBox

Changeset 88265 in vbox for trunk/include/VBox


Ignore:
Timestamp:
Mar 24, 2021 6:24:50 AM (4 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
143470
Message:

Intel IOMMU: bugref:9967 WIP.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/iommu-intel.h

    r88257 r88265  
    3636/**
    3737 * @name MMIO register offsets.
    38  * In accordance with the AMD spec.
     38 * In accordance with the Intel spec.
    3939 * @{
    4040 */
    … …  
    685685
    686686/** @name Version Register (VER_REG).
     687 * In accordance with the Intel spec.
    687688 *  @{ */
    688689/** Min: Minor Version Number. */
    … …  
    703704
    704705/** @name Capability Register (CAP_REG).
     706 * In accordance with the Intel spec.
    705707 * @{ */
    706708/** ND: Number of domains supported. */
    … …  
    786788
    787789/** @name Extended Capability Register (ECAP_REG).
     790 * In accordance with the Intel spec.
    788791 * @{ */
    789792/** C: Page-walk Coherence. */
    … …  
    900903
    901904/** @name Global Command Register (GCMD_REG).
     905 * In accordance with the Intel spec.
    902906 * @{ */
    903907/** R: Reserved (bits 22:0). */
    … …  
    940944
    941945/** @name Global Status Register (GSTS_REG).
     946 * In accordance with the Intel spec.
    942947 * @{ */
    943948/** R: Reserved (bits 22:0). */
    … …  
    980985
    981986/** @name Root Table Address Register (RTADDR_REG).
     987 * In accordance with the Intel spec.
    982988 * @{ */
    983989/** R: Reserved (bits 9:0). */
    … …  
    9991005
    10001006/** @name Context Command Register (CCMD_REG).
     1007 * In accordance with the Intel spec.
    10011008 * @{ */
    10021009/** DID: Domain-ID. */
    … …  
    10321039
    10331040/** @name IOTLB Invalidation Register (IOTLB_REG).
     1041 * In accordance with the Intel spec.
    10341042 * @{ */
    10351043/** R: Reserved (bits 31:0). */
    … …  
    10741082
    10751083/** @name Invalidate Address Register (IVA_REG).
     1084 * In accordance with the Intel spec.
    10761085 * @{ */
    10771086/** AM: Address Mask. */
    … …  
    10971106
    10981107/** @name Fault Status Register (FSTS_REG).
     1108 * In accordance with the Intel spec.
    10991109 * @{ */
    11001110/** PFO: Primary Fault Overflow. */
    … …  
    11431153
    11441154/** @name Fault Event Control Register (FECTL_REG).
     1155 * In accordance with the Intel spec.
    11451156 * @{ */
    11461157/** R: Reserved (bits 29:0). */
    … …  
    11621173
    11631174/** @name Fault Event Data Register (FEDATA_REG).
     1175 * In accordance with the Intel spec.
    11641176 * @{ */
    11651177/** IMD: Interrupt Message Data. */
    … …  
    11781190
    11791191/** @name Fault Event Address Register (FEADDR_REG).
     1192 * In accordance with the Intel spec.
    11801193 * @{ */
    11811194/** R: Reserved (bits 1:0). */
    … …  
    11941207
    11951208/** @name Fault Event Upper Address Register (FEUADDR_REG).
     1209 * In accordance with the Intel spec.
    11961210 * @{ */
    11971211/** MUA: Message Upper Address. */
    … …  
    12051219
    12061220/** @name Fault Recording Register (FRCD_REG).
     1221 * In accordance with the Intel spec.
    12071222 * @{ */
    12081223/** R: Reserved (bits 11:0). */
    … …  
    12611276
    12621277/** @name Advanced Fault Log Register (AFLOG_REG).
     1278 * In accordance with the Intel spec.
    12631279 * @{ */
    12641280/** R: Reserved (bits 8:0). */
    … …  
    12801296
    12811297/** @name Protected Memory Enable Register (PMEN_REG).
     1298 * In accordance with the Intel spec.
    12821299 * @{ */
    12831300/** PRS: Protected Region Status. */
    … …  
    12991316
    13001317/** @name Invalidation Queue Head Register (IQH_REG).
     1318 * In accordance with the Intel spec.
    13011319 * @{ */
    13021320/** R: Reserved (bits 3:0). */
    … …  
    13181336
    13191337/** @name Invalidation Queue Tail Register (IQT_REG).
     1338 * In accordance with the Intel spec.
    13201339 * @{ */
    13211340/** R: Reserved (bits 3:0). */
    … …  
    13371356
    13381357/** @name Invalidation Queue Address Register (IQA_REG).
     1358 * In accordance with the Intel spec.
    13391359 * @{ */
    13401360/** QS: Queue Size. */
    … …  
    13601380
    13611381/** @name Invalidation Completion Status Register (ICS_REG).
     1382 * In accordance with the Intel spec.
    13621383 * @{ */
    13631384/** IWC: Invalidation Wait Descriptor Complete. */
    … …  
    13781399
    13791400/** @name Invalidation Event Control Register (IECTL_REG).
     1401 * In accordance with the Intel spec.
    13801402 * @{ */
    13811403/** R: Reserved (bits 29:0). */
    … …  
    13971419
    13981420/** @name Invalidation Event Data Register (IEDATA_REG).
     1421 * In accordance with the Intel spec.
    13991422 * @{ */
    14001423/** IMD: Interrupt Message Data. */
    … …  
    14131436
    14141437/** @name Invalidation Event Address Register (IEADDR_REG).
     1438 * In accordance with the Intel spec.
    14151439 * @{ */
    14161440/** R: Reserved (bits 1:0). */
    … …  
    14401464
    14411465/** @name Invalidation Queue Error Record Register (IQERCD_REG).
     1466 * In accordance with the Intel spec.
    14421467 * @{ */
    14431468/** IQEI: Invalidation Queue Error Info. */
    … …  
    14621487
    14631488/** @name Interrupt Remapping Table Address Register (IRTA_REG).
     1489 * In accordance with the Intel spec.
    14641490 * @{ */
    14651491/** S: Size. */
    … …  
    14851511
    14861512/** @name Page Request Queue Head Register (PQH_REG).
     1513 * In accordance with the Intel spec.
    14871514 * @{ */
    14881515/** R: Reserved (bits 4:0). */
    … …  
    15041531
    15051532/** @name Page Request Queue Tail Register (PQT_REG).
     1533 * In accordance with the Intel spec.
    15061534 * @{ */
    15071535/** R: Reserved (bits 4:0). */
    … …  
    15231551
    15241552/** @name Page Request Queue Address Register (PQA_REG).
     1553 * In accordance with the Intel spec.
    15251554 * @{ */
    15261555/** PQS: Page Queue Size. */
    … …  
    15421571
    15431572/** @name Page Request Status Register (PRS_REG).
     1573 * In accordance with the Intel spec.
    15441574 * @{ */
    15451575/** PPR: Pending Page Request. */
    … …  
    15631593
    15641594/** @name Page Request Event Control Register (PECTL_REG).
     1595 * In accordance with the Intel spec.
    15651596 * @{ */
    15661597/** R: Reserved (bits 29:0). */
    … …  
    15821613
    15831614/** @name Page Request Event Data Register (PEDATA_REG).
     1615 * In accordance with the Intel spec.
    15841616 * @{ */
    15851617/** IMD: Interrupt Message Data. */
    … …  
    15981630
    15991631/** @name Page Request Event Address Register (PEADDR_REG).
     1632 * In accordance with the Intel spec.
    16001633 * @{ */
    16011634/** R: Reserved (bits 1:0). */
    … …  
    16151648
    16161649/** @name Page Request Event Upper Address Register (PEUADDR_REG).
     1650 * In accordance with the Intel spec.
    16171651 * @{ */
    16181652/** MA: Message Address. */
    … …  
    16261660
    16271661/** @name MTRR Capability Register (MTRRCAP_REG).
     1662 * In accordance with the Intel spec.
    16281663 * @{ */
    16291664/** VCNT: Variable MTRR Count. */
    … …  
    16511686
    16521687/** @name MTRR Default Type Register (MTRRDEF_REG).
     1688 * In accordance with the Intel spec.
    16531689 * @{ */
    16541690/** TYPE: Default Memory Type. */
    … …  
    16771713
    16781714/** @name Virtual Command Capability Register (VCCAP_REG).
     1715 * In accordance with the Intel spec.
    16791716 * @{ */
    16801717/** PAS: PASID Support. */
    … …  
    16931730
    16941731/** @name Virtual Command Register (VCMD_REG).
     1732 * In accordance with the Intel spec.
    16951733 * @{ */
    16961734/** CMD: Command. */
    … …  
    17091747
    17101748/** @name Virtual Command Response Register (VCRSP_REG).
     1749 * In accordance with the Intel spec.
    17111750 * @{ */
    17121751/** IP: In Progress. */
    … …  
    17301769
    17311770
     1771/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
     1772 * In accordance with the Intel spec.
     1773 * @{ */
     1774/** INTR_REMAP: Interrupt remapping supported. */
     1775#define ACPI_DMAR_F_INTR_REMAP                                  RT_BIT(0)
     1776/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
     1777#define ACPI_DMAR_F_X2APIC_OPT_OUT                              RT_BIT(0)
     1778/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
     1779 *  memory regions (RMRR). */
     1780#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN                    RT_BIT(2)
     1781/** @} */
     1782
     1783
     1784/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
     1785 * In accordance with the Intel spec.
     1786 * @{ */
     1787/** INCLUDE_PCI_ALL: All PCI devices under scope. */
     1788#define ACPI_DRHD_F_INCLUDE_PCI_ALL                             RT_BIT(0)
     1789/** @} */
     1790
     1791
     1792/**
     1793 * DRHD: DMA-Remapping Hardware Unit Definition.
     1794 * In accordance with the Intel spec.
     1795 */
     1796#pragma pack(1)
     1797typedef struct ACPIDRHD
     1798{
     1799    /** Type (must be 0=DRHD). */
     1800    uint16_t        uType;
     1801    /** Length (must be 16 + size of device scope structure). */
     1802    uint16_t        cbLength;
     1803    /** Flags, see ACPI_DMAR_F_XXX. */
     1804    uint8_t         fFlags;
     1805    /** Reserved (MBZ). */
     1806    uint8_t         bRsvd;
     1807    /** PCI segment number. */
     1808    uint16_t        uPciSegment;
     1809    /** Register Base Address (MMIO). */
     1810    uint64_t        uRegBaseAddr;
     1811    /* Device Scope[] Structures follow. */
     1812} ACPIDRHD;
     1813#pragma pack()
     1814AssertCompileSize(ACPIDRHD, 16);
     1815AssertCompileMemberOffset(ACPIDRHD, cbLength,     2);
     1816AssertCompileMemberOffset(ACPIDRHD, fFlags,       4);
     1817AssertCompileMemberOffset(ACPIDRHD, uPciSegment,  6);
     1818AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
     1819
     1820
     1821/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
     1822 * In accordance with the Intel spec.
     1823 * @{ */
     1824#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT                      1
     1825#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY                 2
     1826#define ACPIDMARDEVSCOPE_TYPE_IOAPIC                            3
     1827#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET                      4
     1828#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV                5
     1829/** @} */
     1830
     1831
     1832/**
     1833 * Device Scope Structure.
     1834 * In accordance with the Intel spec.
     1835 */
     1836#pragma pack(1)
     1837typedef struct ACPIDMARDEVSCOPE
     1838{
     1839    /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
     1840    uint8_t         uType;
     1841    /** Length (must be 6 + size of auPath field).  */
     1842    uint8_t         cbLength;
     1843    /** Reserved (MBZ). */
     1844    uint8_t         abRsvd[2];
     1845    /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
     1846    uint8_t         idEnum;
     1847    /** First bus number for this device. */
     1848    uint8_t         uStartBusNum;
     1849    /** Hierarchical path from the Host Bridge to the device. */
     1850    uint16_t        auPath[1];
     1851} ACPIDMARDEVSCOPE;
     1852#pragma pack()
     1853AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength,     1);
     1854AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum,       4);
     1855AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
     1856AssertCompileMemberOffset(ACPIDMARDEVSCOPE, auPath,       6);
     1857
     1858
    17321859#endif /* !VBOX_INCLUDED_iommu_intel_h */
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