Changeset 88281 in vbox for trunk/src/VBox/Devices/PC

Timestamp:

Mar 24, 2021 3:03:53 PM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 ACPI: Adjustments for Intel IOMMU (DMAR). WIP.

File:

• trunk/src/VBox/Devices/PC/DevACPI.cpp (modified) (12 diffs)

trunk/src/VBox/Devices/PC/DevACPI.cpp

@@ -39 +39 @@
 #ifdef VBOX_WITH_IOMMU_AMD
 # include <VBox/iommu-amd.h>
+#endif
+#ifdef VBOX_WITH_IOMMU_INTEL
+# include <VBox/iommu-intel.h>
 #endif
 
@@ -372 +375 @@
     /** if the 64-bit prefetchable memory window is shown to the guest */
     bool                fPciPref64Enabled;
-    /** If the IOMMU device should be enabled */
-    bool                fUseIommu;
+    /** If the IOMMU (AMD) device should be enabled */
+    bool                fUseIommuAmd;
+    /** If the IOMMU (Intel) device should be enabled */
+    bool                fUseIommuIntel;
+    /** Padding. */
+    bool                afPadding0[3];
     /** Primary NIC PCI address. */
     uint32_t            u32NicPciAddress;
@@ -829 +836 @@
 AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
 AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
-#endif
+#endif  /* VBOX_WITH_IOMMU_AMD */
+
+#ifdef VBOX_WITH_IOMMU_INTEL
+/** Intel IOMMU: DMAR (DMA Remapping) Reporting Structure.
+ *  In accordance with the AMD spec. */
+typedef struct ACPIDMAR
+{
+    ACPITBLHEADER       Hdr;
+    /** Host-address Width (N+1 physical bits addressable). */
+    uint8_t             uHostAddrWidth;
+    /** Flags, see ACPI_DMAR_F_XXX. */
+    uint8_t             fFlags;
+    /** Reserved. */
+    uint8_t             abRsvd[10];
+    /* Remapping Structures[] follows. */
+} ACPIDMAR;
+AssertCompileSize(ACPIDMAR, 48);
+AssertCompileMemberOffset(ACPIDMAR, uHostAddrWidth, 36);
+AssertCompileMemberOffset(ACPIDMAR, fFlags, 37);
+
+/**
+ * Intel VT-d: The ACPI table.
+ */
+typedef struct ACPITBLVTD
+{
+    ACPIDMAR            Dmar;
+    ACPIDRHD            Drhd;
+} ACPITBLDMAR;
+#endif  /* VBOX_WITH_IOMMU_INTEL */
 
 /** MCFG Descriptor Structure */
@@ -3316 +3351 @@
     Ivrs.IvhdType11Hpet   = Ivrs.IvhdType10Hpet;
 
-    /* Finally, Compute checksum. */
+    /* Finally, compute checksum. */
     Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
 
     /* Plant the ACPI table. */
     acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
+}
+#endif
+
+
+#ifdef VBOX_WITH_IOMMU_INTEL
+/**
+ * Plant the Intel IOMMU (VT-d) descriptor.
+ */
+static void acpiR3SetupIommuIntel(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
+{
+    ACPITBLVTD VtdTable;
+    RT_ZERO(VtdTable);
+
+    /* VT-d/DMAR header. */
+    acpiR3PrepareHeader(pThis, &VtdTable.Dmar.Hdr, "DMAR", sizeof(ACPITBLVTD), ACPI_DMAR_REVISION);
+
+    /** @todo Populate rest of DMAR table. */
+
+    /* Finally, compute checksum. */
+    VtdTable.Dmar.Hdr.u8Checksum = acpiR3Checksum(&VtdTable, sizeof(VtdTable));
+
+    /* Plant the ACPI table. */
+    acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&VtdTable, sizeof(VtdTable));
 }
 #endif
@@ -3424 +3482 @@
     RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
     RTGCPHYS32 GCPhysHpet = 0;
-#ifdef VBOX_WITH_IOMMU_AMD
-    RTGCPHYS32 GCPhysIommuAmd = 0;
+#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
+    RTGCPHYS32 GCPhysIommu = 0;
 #endif
     RTGCPHYS32 GCPhysApic = 0;
@@ -3432 +3490 @@
     RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
     uint32_t   addend = 0;
-#ifdef VBOX_WITH_IOMMU_AMD
+#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
     RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
     RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
@@ -3442 +3500 @@
     uint32_t   iMadt  = 0;
     uint32_t   iHpet  = 0;
-#ifdef VBOX_WITH_IOMMU_AMD
-    uint32_t   iIommuAmd = 0;
+#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
+    uint32_t   iIommu = 0;
 #endif
     uint32_t   iSsdt  = 0;
@@ -3459 +3517 @@
 
 #ifdef VBOX_WITH_IOMMU_AMD
-    if (pThis->fUseIommu)
-        iIommuAmd = cAddr++;    /* IOMMU (AMD) */
+    if (pThis->fUseIommuAmd)
+        iIommu = cAddr++;      /* IOMMU (AMD) */
+#endif
+
+#ifdef VBOX_WITH_IOMMU_INTEL
+    if (pThis->fUseIommuIntel)
+        iIommu = cAddr++;      /* IOMMU (AMD) */
 #endif
 
@@ -3538 +3601 @@
     }
 #ifdef VBOX_WITH_IOMMU_AMD
-    if (pThis->fUseIommu)
-    {
-        GCPhysIommuAmd = GCPhysCur;
+    if (pThis->fUseIommuAmd)
+    {
+        GCPhysIommu = GCPhysCur;
         GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
     }
 #endif
+#ifdef VBOX_WITH_IOMMU_INTEL
+    if (pThis->fUseIommuIntel)
+    {
+        GCPhysIommu = GCPhysCur;
+        GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLVTD), 16);
+    }
+#endif
+
     if (pThis->fUseMcfg)
     {
@@ -3617 +3688 @@
     }
 #ifdef VBOX_WITH_IOMMU_AMD
-    if (pThis->fUseIommu)
-    {
-        acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommuAmd + addend);
-        aGCPhysRsdt[iIommuAmd] = GCPhysIommuAmd + addend;
-        aGCPhysXsdt[iIommuAmd] = GCPhysIommuAmd + addend;
+    if (pThis->fUseIommuAmd)
+    {
+        acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommu + addend);
+        aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
+        aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
+    }
+#endif
+#ifdef VBOX_WITH_IOMMU_INTEL
+    if (pThis->fUseIommuIntel)
+    {
+        acpiR3SetupIommuIntel(pDevIns, pThis, GCPhysIommu + addend);
+        aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
+        aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
     }
 #endif
@@ -4140 +4219 @@
 
 #ifdef VBOX_WITH_IOMMU_AMD
-    /* Query whether an IOMMU AMD is enabled. */
-    rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommu, false);
+    /* Query whether an IOMMU (AMD) is enabled. */
+    rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommuAmd, false);
     if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuEnabled\""));
-
-    if (pThis->fUseIommu)
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdEnabled\""));
+
+    if (pThis->fUseIommuAmd)
     {
         /* Query IOMMU AMD address (IOMA). */
@@ -4172 +4251 @@
     }
 #endif
+
+#ifdef VBOX_WITH_IOMMU_INTEL
+    /* Query whether an IOMMU (Intel) is enabled. */
+    rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuIntelEnabled", &pThis->fUseIommuIntel, false);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
+#endif
+
+    /* Don't even think about enabling an Intel and an AMD IOMMU at the same time! */
+    if (   pThis->fUseIommuAmd
+        && pThis->fUseIommuIntel)
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Cannot enable Intel and AMD IOMMU simultaneously!"));
 
     /* Try to attach the other CPUs */