Changeset 88333 in vbox for trunk/src/VBox/Devices/PC

Timestamp:

Mar 31, 2021 4:29:39 PM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 ACPI, BusAssignmentManager and ConsoleImpl2 changes for VT-d PCI device.

File:

• trunk/src/VBox/Devices/PC/DevACPI.cpp (modified) (9 diffs)

trunk/src/VBox/Devices/PC/DevACPI.cpp

@@ -209 +209 @@
     SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
     SYSTEM_INFO_INDEX_NVME_ADDRESS      = 31, /**< First NVMe controller PCI address, or 0 */
-    SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS = 32, /**< AMD IOMMU PCI address, or 0 */
+    SYSTEM_INFO_INDEX_IOMMU_ADDRESS     = 32, /**< IOMMU PCI address, or 0 */
     SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
     SYSTEM_INFO_INDEX_END               = 34,
@@ -402 +402 @@
     /** PCI address of the host bus controller device. */
     uint32_t            u32HbcPciAddress;
-    /** PCI address of the AMD IOMMU device. */
-    uint32_t            u32IommuAmdPciAddress;
+    /** PCI address of the IOMMU device. */
+    uint32_t            u32IommuPciAddress;
     /** PCI address of the southbridge I/O APIC device. */
     uint32_t            u32SbIoApicPciAddress;
@@ -1655 +1655 @@
             break;
 
-        case SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS:
-            *pu32 = pThis->u32IommuAmdPciAddress;
+        case SYSTEM_INFO_INDEX_IOMMU_ADDRESS:
+            *pu32 = pThis->u32IommuPciAddress;
             break;
 
@@ -3220 +3220 @@
 
     uint16_t const uIommuBus = 0;
-    uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuAmdPciAddress);
-    uint16_t const uIommuFn  = RT_LO_U16(pThis->u32IommuAmdPciAddress);
+    uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuPciAddress);
+    uint16_t const uIommuFn  = RT_LO_U16(pThis->u32IommuPciAddress);
 
     /* IVRS header. */
@@ -3387 +3387 @@
     VtdTable.Drhd.cbLength     = sizeof(ACPIDRHD) /* + sizeof(VtdTable.DevScope) */;
     VtdTable.Drhd.fFlags       = ACPI_DRHD_F_INCLUDE_PCI_ALL;
-    VtdTable.Drhd.uRegBaseAddr = VTD_MMIO_BASE_ADDR;
+    VtdTable.Drhd.uRegBaseAddr = VTD_MMIO_BASE_PHYSADDR;
 
     /* Finally, compute checksum. */
@@ -4074 +4074 @@
                                   "|Parallel0Irq"
                                   "|Parallel1Irq"
+                                  "|IommuIntelEnabled"
                                   "|IommuAmdEnabled"
-                                  "|IommuAmdPciAddress"
+                                  "|IommuPciAddress"
                                   "|SbIoApicPciAddress"
                                   , "");
@@ -4242 +4243 @@
     {
         /* Query IOMMU AMD address (IOMA). */
-        rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuAmdPciAddress", &pThis->u32IommuAmdPciAddress, 0);
+        rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress, 0);
         if (RT_FAILURE(rc))
-            return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdAddress\""));
+            return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
 
         /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
@@ -4254 +4255 @@
         /** @todo We should eventually not assign the IOMMU at this address, see
          *        @bugref{9654#c53}. */
-        if (!pThis->u32IommuAmdPciAddress)
+        if (!pThis->u32IommuPciAddress)
             LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
 
@@ -4272 +4273 @@
     if (RT_FAILURE(rc))
         return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
+
+    if (pThis->fUseIommuIntel)
+    {
+        /* Query IOMMU Intel address. */
+        rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress, 0);
+        if (RT_FAILURE(rc))
+            return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
+    }
 #endif