Changeset 88414 in vbox
- Timestamp:
- Apr 8, 2021 12:04:06 PM (4 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r88407 r88414 792 792 | RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */ 793 793 | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, 0) /* 0 as Second-level Translation not supported. */ 794 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, cGstPhysAddrBits )794 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, cGstPhysAddrBits - 1) 795 795 | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Zero-length read? */ 796 796 | RT_BF_MAKE(VTD_BF_CAP_REG_FRO, DMAR_MMIO_OFF_FRCD_LO_REG >> 4) … … 856 856 /* FECTL_REG */ 857 857 { 858 uint32_t const u Reg= RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);859 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, u Reg);858 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1); 859 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl); 860 860 } 861 861 /* ICETL_REG */ 862 862 { 863 uint32_t const u Reg= RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);864 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, u Reg);863 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1); 864 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl); 865 865 } 866 866 … … 1011 1011 dmarR3RegsInit(pDevIns); 1012 1012 1013 LogRel(("%s: Capabilities=%#RX64 Extended-Capabilities=%#RX64\n", DMAR_LOG_PFX, dmarRegRead64(pThis, VTD_MMIO_OFF_CAP_REG), 1014 dmarRegRead64(pThis, VTD_MMIO_OFF_ECAP_REG))); 1013 uint64_t const fCap = dmarRegRead64(pThis, VTD_MMIO_OFF_CAP_REG); 1014 uint64_t const fExtCap = dmarRegRead64(pThis, VTD_MMIO_OFF_ECAP_REG); 1015 uint8_t const uMaxGstAddrWidth = RT_BF_GET(fCap, VTD_BF_CAP_REG_MGAW) + 1; 1016 LogRel(("%s: CAP=%#RX64 ECAP=%#RX64 (MGAW=%u)\n", DMAR_LOG_PFX, fCap, fExtCap, uMaxGstAddrWidth)); 1015 1017 return VINF_SUCCESS; 1016 1018 }
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