Changeset 88515 in vbox for trunk

Timestamp:

Apr 15, 2021 5:36:29 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 Push IOTLB and FRCD registers beyond 0xe4f which according to the 2021 VT-d spec is reserved.

Location:

trunk

Files:

• include/VBox/iommu-intel.h (modified) (1 diff)
• src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (5 diffs)

trunk/include/VBox/iommu-intel.h

@@ -1736 +1736 @@
 
 
+/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
+ * In accordance with the Intel spec.
+ * @{ */
+/** OB: Operand B. */
+#define VTD_BF_VCMD_EO_REG_OB_SHIFT                             0
+#define VTD_BF_VCMD_EO_REG_OB_MASK                              UINT32_C(0xffffffffffffffff)
+
+/** RW: Read/write mask. */
+#define VTD_VCMD_EO_REG_RW_MASK                                 VTD_BF_VCMD_EO_REG_OB_MASK
+/** @} */
+
+
 /** @name Virtual Command Register (VCMD_REG).
  * In accordance with the Intel spec.

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -72 +72 @@
 #define DMAR_MMIO_GROUP_0_SIZE                      (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
 /**< Implementation-specific MMIO offset of IVA_REG. */
-#define DMAR_MMIO_OFF_IVA_REG                       0xe40
+#define DMAR_MMIO_OFF_IVA_REG                       0xe50
 /**< Implementation-specific MMIO offset of IOTLB_REG. */
-#define DMAR_MMIO_OFF_IOTLB_REG                     0xe48
+#define DMAR_MMIO_OFF_IOTLB_REG                     0xe58
    /**< Implementation-specific MMIO offset of FRCD_LO_REG. */
-#define DMAR_MMIO_OFF_FRCD_LO_REG                   0xe60
+#define DMAR_MMIO_OFF_FRCD_LO_REG                   0xe70
 /**< Implementation-specific MMIO offset of FRCD_HI_REG. */
-#define DMAR_MMIO_OFF_FRCD_HI_REG                   0xe68
+#define DMAR_MMIO_OFF_FRCD_HI_REG                   0xe78
 AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
 
@@ -397 +397 @@
     /* Offset  Register                  Low                                        High */
     /* 0xe00   VCCAP_REG             */  DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK),        DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
-    /* 0xe08   Reserved              */  0,                                         0,
+    /* 0xe08   VCMD_EO_REG           */  DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK),      DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
     /* 0xe10   VCMD_REG              */  0,                                         0, /* RO: VCS not supported. */
     /* 0xe18   VCMDRSVD_REG          */  0,                                         0,
@@ -404 +404 @@
     /* 0xe30   Reserved              */  0,                                         0,
     /* 0xe38   Reserved              */  0,                                         0,
-    /* 0xe40   IVA_REG               */  DMAR_LO_U32(VTD_IVA_REG_RW_MASK),          DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
-    /* 0xe48   IOTLB_REG             */  DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK),        DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
-    /* 0xe50   Reserved              */  0,                                         0,
-    /* 0xe58   Reserved              */  0,                                         0,
-    /* 0xe60   FRCD_REG_LO           */  DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK),      DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
-    /* 0xe68   FRCD_REG_HI           */  DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK),      DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
+    /* 0xe40   Reserved              */  0,                                         0,
+    /* 0xe48   Reserved              */  0,                                         0,
+    /* 0xe50   IVA_REG               */  DMAR_LO_U32(VTD_IVA_REG_RW_MASK),          DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
+    /* 0xe58   IOTLB_REG             */  DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK),        DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
+    /* 0xe60   Reserved              */  0,                                         0,
+    /* 0xe68   Reserved              */  0,                                         0,
+    /* 0xe70   FRCD_REG_LO           */  DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK),      DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
+    /* 0xe78   FRCD_REG_HI           */  DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK),      DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
 };
 AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
@@ -421 +423 @@
     /* Offset  Register                  Low                                        High */
     /* 0xe00   VCCAP_REG             */  0,                                         0,
-    /* 0xe08   Reserved              */  0,                                         0,
+    /* 0xe08   VCMD_EO_REG           */  0,                                         0,
     /* 0xe10   VCMD_REG              */  0,                                         0,
     /* 0xe18   VCMDRSVD_REG          */  0,                                         0,
@@ -428 +430 @@
     /* 0xe30   Reserved              */  0,                                         0,
     /* 0xe38   Reserved              */  0,                                         0,
-    /* 0xe40   IVA_REG               */  0,                                         0,
-    /* 0xe48   IOTLB_REG             */  0,                                         0,
-    /* 0xe50   Reserved              */  0,                                         0,
-    /* 0xe58   Reserved              */  0,                                         0,
-    /* 0xe60   FRCD_REG_LO           */  DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK),    DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
-    /* 0xe68   FRCD_REG_HI           */  DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK),    DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
+    /* 0xe40   Reserved              */  0,                                         0,
+    /* 0xe48   Reserved              */  0,                                         0,
+    /* 0xe50   IVA_REG               */  0,                                         0,
+    /* 0xe58   IOTLB_REG             */  0,                                         0,
+    /* 0xe60   Reserved              */  0,                                         0,
+    /* 0xe68   Reserved              */  0,                                         0,
+    /* 0xe70   FRCD_REG_LO           */  DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK),    DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
+    /* 0xe78   FRCD_REG_HI           */  DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK),    DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
 };
 AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);