Changeset 88590 in vbox

Timestamp:

Apr 20, 2021 2:49:16 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: WIP.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (14 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -131 +131 @@
  * DMAR error diagnostics.
  *
- * @note Members of this enum are used as array indices, so no gaps are allowed.
- *       Please update g_apsz when you add new fields to this enum.
+ * @note Members of this enum are used as array indices, so no gaps in enum
+ *       values are not allowed. Update g_apszDmarDiagDesc when you modify
+ *       fields in this enum.
  */
 typedef enum
@@ -211 +212 @@
 typedef DMAR *PDMAR;
 /** Pointer to the const DMAR device state. */
-typedef const DMAR *PCDMAR;
+typedef DMAR const *PCDMAR;
 
 /**
@@ -226 +227 @@
 typedef DMARR3 *PDMARR3;
 /** Pointer to the const ring-3 DMAR device state. */
-typedef const DMARR3 *PCDMARR3;
+typedef DMARR3 const *PCDMARR3;
 
 /**
@@ -241 +242 @@
 typedef DMARR0 *PDMARR0;
 /** Pointer to the const ring-0 IOMMU device state. */
-typedef const DMARR0 *PCDMARR0;
+typedef DMARR0 const *PCDMARR0;
 
 /**
@@ -256 +257 @@
 typedef DMARRC *PDMARRC;
 /** Pointer to the const raw-mode DMAR device state. */
-typedef const DMARRC *PCIDMARRC;
+typedef DMARRC const *PCIDMARRC;
 
 /** The DMAR device state for the current context. */
@@ -263 +264 @@
 typedef CTX_SUFF(PDMAR) PDMARCC;
 /** Pointer to the const DMAR device state for the current context. */
-typedef const CTX_SUFF(PDMAR) PCDMARCC;
+typedef CTX_SUFF(PDMAR) const PCDMARCC;
 
 
@@ -627 +628 @@
 
 /**
- * Modifies a 32-bit register.
+ * Reads a 32-bit register with exactly the value it contains.
  *
  * @param   pThis       The shared DMAR device state.
@@ -634 +635 @@
  * @param   fOrMask     The OR mask.
  */
-static void dmarRegChange32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
+static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
 {
     uint8_t idxGroup;
-    uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
+    uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
     NOREF(idxGroup);
-    uint32_t uReg = *(uint32_t *)(pabRegs + offReg);
-    uReg = (uReg & fAndMask) | fOrMask;
-    *(uint32_t *)(pabRegs + offReg) = uReg;
-}
-
-
-/**
- * Modifies a 64-bit register.
+    return *(uint32_t *)(pabRegs + offReg);
+}
+
+
+/**
+ * Reads a 64-bit register with exactly the value it contains.
  *
  * @param   pThis       The shared DMAR device state.
  * @param   offReg      The MMIO offset of the register.
- * @param   fAndMask    The AND mask (applied first).
- * @param   fOrMask     The OR mask.
- */
-static void dmarRegChange64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
+ */
+static uint32_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
 {
     uint8_t idxGroup;
-    uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
+    uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
     NOREF(idxGroup);
-    uint64_t uReg = *(uint64_t *)(pabRegs + offReg);
-    uReg = (uReg & fAndMask) | fOrMask;
-    *(uint64_t *)(pabRegs + offReg) = uReg;
-}
-
-
-/**
- * Reads a 64-bit register with exactly the value it contains.
+    return *(uint64_t *)(pabRegs + offReg);
+}
+
+
+/**
+ * Reads a 32-bit register with exactly the value it contains along with their
+ * corresponding masks
+ *
+ * @param   pThis       The shared DMAR device state.
+ * @param   offReg      The MMIO offset of the register.
+ * @param   puReg       Where to store the raw 32-bit register value.
+ * @param   pfRwMask    Where to store the RW mask corresponding to this register.
+ * @param   pfRw1cMask  Where to store the RW1C mask corresponding to this register.
+ */
+static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
+{
+    uint8_t idxGroup;
+    uint8_t const *pabRegs      = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
+    Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
+    uint8_t const *pabRwMasks   = g_apbRwMasks[idxGroup];
+    uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
+    *puReg      = *(uint32_t *)(pabRegs      + offReg);
+    *pfRwMask   = *(uint32_t *)(pabRwMasks   + offReg);
+    *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
+}
+
+
+/**
+ * Reads a 64-bit register with exactly the value it contains along with their
+ * corresponding masks.
  *
  * @param   pThis       The shared DMAR device state.
@@ -673 +692 @@
  * @param   pfRw1cMask  Where to store the RW1C mask corresponding to this register.
  */
-static void dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
+static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
 {
     uint8_t idxGroup;
@@ -687 +706 @@
 
 /**
- * Reads a 32-bit register with exactly the value it contains.
- *
- * @param   pThis       The shared DMAR device state.
- * @param   offReg      The MMIO offset of the register.
- * @param   puReg       Where to store the raw 32-bit register value.
- * @param   pfRwMask    Where to store the RW mask corresponding to this register.
- * @param   pfRw1cMask  Where to store the RW1C mask corresponding to this register.
- */
-static void dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
-{
-    uint8_t idxGroup;
-    uint8_t const *pabRegs      = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
-    Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
-    uint8_t const *pabRwMasks   = g_apbRwMasks[idxGroup];
-    uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
-    *puReg      = *(uint32_t *)(pabRegs      + offReg);
-    *pfRwMask   = *(uint32_t *)(pabRwMasks   + offReg);
-    *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
-}
-
-
-/**
  * Writes a 64-bit register as it would be when written by software.
  * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
@@ -723 +720 @@
     uint64_t fRwMask;
     uint64_t fRw1cMask;
-    dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
+    dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
 
     uint64_t const fRoBits   = uCurReg & ~fRwMask;      /* Preserve current read-only and reserved bits. */
@@ -751 +748 @@
     uint32_t fRwMask;
     uint32_t fRw1cMask;
-    dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
+    dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
 
     uint32_t const fRoBits   = uCurReg & ~fRwMask;      /* Preserve current read-only and reserved bits. */
@@ -773 +770 @@
 static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
 {
-    uint64_t uCurReg;
-    uint64_t fRwMask;
-    uint64_t fRw1cMask;
-    dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
-    NOREF(fRwMask); NOREF(fRw1cMask);
-    return uCurReg;
+    return dmarRegReadRaw64(pThis, offReg);
 }
 
@@ -791 +783 @@
 static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
 {
-    uint32_t uCurReg;
-    uint32_t fRwMask;
-    uint32_t fRw1cMask;
-    dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
-    NOREF(fRwMask); NOREF(fRw1cMask);
-    return uCurReg;
+    return dmarRegReadRaw32(pThis, offReg);
+}
+
+
+/**
+ * Modifies a 32-bit register.
+ *
+ * @param   pThis       The shared DMAR device state.
+ * @param   offReg      The MMIO offset of the register.
+ * @param   fAndMask    The AND mask (applied first).
+ * @param   fOrMask     The OR mask.
+ * @remarks This does NOT apply RO or RW1C masks while modifying the
+ *          register.
+ */
+static void dmarRegChange32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
+{
+    uint32_t uReg = dmarRegRead32(pThis, offReg);
+    uReg = (uReg & fAndMask) | fOrMask;
+    dmarRegWriteRaw32(pThis, offReg, uReg);
+}
+
+
+/**
+ * Modifies a 64-bit register.
+ *
+ * @param   pThis       The shared DMAR device state.
+ * @param   offReg      The MMIO offset of the register.
+ * @param   fAndMask    The AND mask (applied first).
+ * @param   fOrMask     The OR mask.
+ * @remarks This does NOT apply RO or RW1C masks while modifying the
+ *          register.
+ */
+static void dmarRegChange64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
+{
+    uint64_t uReg = dmarRegRead64(pThis, offReg);
+    uReg = (uReg & fAndMask) | fOrMask;
+    dmarRegWriteRaw64(pThis, offReg, uReg);
 }