VirtualBox

Changeset 88591 in vbox


Ignore:
Timestamp:
Apr 20, 2021 3:30:45 AM (4 years ago)
Author:
vboxsync
Message:

Intel IOMMU: bugref:9967 WIP.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

    r88590 r88591  
    596596
    597597/**
     598 * Writes a 32-bit register with the exactly the supplied value.
     599 *
     600 * @param   pThis   The shared DMAR device state.
     601 * @param   offReg  The MMIO offset of the register.
     602 * @param   uReg    The 32-bit value to write.
     603 */
     604static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
     605{
     606    uint8_t idxGroup;
     607    uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
     608    NOREF(idxGroup);
     609    *(uint32_t *)(pabRegs + offReg) = uReg;
     610}
     611
     612
     613/**
    598614 * Writes a 64-bit register with the exactly the supplied value.
    599615 *
    600  * @param   pThis       The shared DMAR device state.
    601  * @param   offReg      The MMIO offset of the register.
    602  * @param   uReg        The 64-bit value to write.
     616 * @param   pThis   The shared DMAR device state.
     617 * @param   offReg  The MMIO offset of the register.
     618 * @param   uReg    The 64-bit value to write.
    603619 */
    604620static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
     
    612628
    613629/**
    614  * Writes a 32-bit register with the exactly the supplied value.
    615  *
    616  * @param   pThis       The shared DMAR device state.
    617  * @param   offReg      The MMIO offset of the register.
    618  * @param   uReg        The 32-bit value to write.
    619  */
    620 static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
    621 {
    622     uint8_t idxGroup;
    623     uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
    624     NOREF(idxGroup);
    625     *(uint32_t *)(pabRegs + offReg) = uReg;
    626 }
    627 
    628 
    629 /**
    630630 * Reads a 32-bit register with exactly the value it contains.
    631631 *
    632  * @param   pThis       The shared DMAR device state.
    633  * @param   offReg      The MMIO offset of the register.
    634  * @param   fAndMask    The AND mask (applied first).
    635  * @param   fOrMask     The OR mask.
     632 * @param   pThis   The shared DMAR device state.
     633 * @param   offReg  The MMIO offset of the register.
    636634 */
    637635static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
     
    647645 * Reads a 64-bit register with exactly the value it contains.
    648646 *
    649  * @param   pThis       The shared DMAR device state.
    650  * @param   offReg      The MMIO offset of the register.
     647 * @param   pThis   The shared DMAR device state.
     648 * @param   offReg  The MMIO offset of the register.
    651649 */
    652650static uint32_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
     
    706704
    707705/**
     706 * Writes a 32-bit register as it would be when written by software.
     707 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
     708 *
     709 * @returns The value that's actually written to the register.
     710 * @param   pThis   The shared DMAR device state.
     711 * @param   offReg  The MMIO offset of the register.
     712 * @param   uReg    The 32-bit value to write.
     713 */
     714static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
     715{
     716    /* Read current value from the 32-bit register. */
     717    uint32_t uCurReg;
     718    uint32_t fRwMask;
     719    uint32_t fRw1cMask;
     720    dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
     721
     722    uint32_t const fRoBits   = uCurReg & ~fRwMask;      /* Preserve current read-only and reserved bits. */
     723    uint32_t const fRwBits   = uReg & fRwMask;          /* Merge newly written read/write bits. */
     724    uint32_t const fRw1cBits = uReg & fRw1cMask;        /* Clear 1s written to RW1C bits. */
     725    uint32_t const uNewReg   = (fRoBits | fRwBits) & ~fRw1cBits;
     726
     727    /* Write new value to the 32-bit register. */
     728    dmarRegWriteRaw32(pThis, offReg, uNewReg);
     729    return uNewReg;
     730}
     731
     732
     733/**
    708734 * Writes a 64-bit register as it would be when written by software.
    709735 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
     
    734760
    735761/**
    736  * Writes a 32-bit register as it would be when written by software.
    737  * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
    738  *
    739  * @returns The value that's actually written to the register.
     762 * Reads a 32-bit register as it would be when read by software.
     763 *
     764 * @returns The 32-bit register value.
    740765 * @param   pThis   The shared DMAR device state.
    741766 * @param   offReg  The MMIO offset of the register.
    742  * @param   uReg    The 32-bit value to write.
    743  */
    744 static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
    745 {
    746     /* Read current value from the 32-bit register. */
    747     uint32_t uCurReg;
    748     uint32_t fRwMask;
    749     uint32_t fRw1cMask;
    750     dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
    751 
    752     uint32_t const fRoBits   = uCurReg & ~fRwMask;      /* Preserve current read-only and reserved bits. */
    753     uint32_t const fRwBits   = uReg & fRwMask;          /* Merge newly written read/write bits. */
    754     uint32_t const fRw1cBits = uReg & fRw1cMask;        /* Clear 1s written to RW1C bits. */
    755     uint32_t const uNewReg   = (fRoBits | fRwBits) & ~fRw1cBits;
    756 
    757     /* Write new value to the 32-bit register. */
    758     dmarRegWriteRaw32(pThis, offReg, uNewReg);
    759     return uNewReg;
     767 */
     768static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
     769{
     770    return dmarRegReadRaw32(pThis, offReg);
    760771}
    761772
     
    771782{
    772783    return dmarRegReadRaw64(pThis, offReg);
    773 }
    774 
    775 
    776 /**
    777  * Reads a 32-bit register as it would be when read by software.
    778  *
    779  * @returns The 32-bit register value.
    780  * @param   pThis   The shared DMAR device state.
    781  * @param   offReg  The MMIO offset of the register.
    782  */
    783 static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
    784 {
    785     return dmarRegReadRaw32(pThis, offReg);
    786784}
    787785
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