Changeset 88600 in vbox for trunk/src/VBox/Devices

Timestamp:

Apr 20, 2021 11:23:33 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 IQA WIP.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (8 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -139 +139 @@
     kDmarDiag_None = 0,
     kDmarDiag_IqtReg_Qt_NotAligned,
+    kDmarDiag_IqaReg_Dw_Invalid,
     /* Last member for determining array index limit. */
     kDmarDiag_End
@@ -150 +151 @@
 static const char *const g_apszDmarDiagDesc[] =
 {
-    DMARDIAG_DESC(kNone,                            "None"                ),
-    DMARDIAG_DESC(kDmarDiag_IqtReg_Qt_NotAligned,   "IqtReg_Qt_NotAligned")
+    DMARDIAG_DESC(kNone                         , "None"                ),
+    DMARDIAG_DESC(kDmarDiag_IqtReg_Qt_NotAligned, "IqtReg_Qt_NotAligned"),
+    DMARDIAG_DESC(kDmarDiag_IqaReg_Dw_Invalid   , "IqaReg_Dw_Invalid"   )
     /* kDmarDiag_End */
 };
@@ -841 +843 @@
  * @param   pThisCC     The current-context DMAR device state.
  */
-static void dmarFaultRaiseInterrupt(PPDMDEVINS pDevIns, PDMAR pThis, PCDMARCC pThisCC)
-{
+static void dmarFaultRaiseInterrupt(PPDMDEVINS pDevIns)
+{
+    PDMAR    pThis   = PDMDEVINS_2_DATA(pDevIns, PDMAR);
+    PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
 #ifdef RT_STRICT
     {
@@ -918 +922 @@
 
 /**
- * Records an IQE (invalidation queue error) fault.
+ * Records an IQE fault.
  *
  * @param   pDevIns     The IOMMU device instance.
@@ -941 +945 @@
     dmarRegChange64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
 
-    dmarFaultRaiseInterrupt(pDevIns, pThis, pThisCC);
+    dmarFaultRaiseInterrupt(pDevIns);
 }
 
@@ -956 +960 @@
 static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t off, uint8_t cb, uint64_t uCcmdReg)
 {
-    /* We only care about responding to high 32-bits writes, low 32-bits are data. */
+    /* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
     if (off + cb > VTD_MMIO_OFF_CCMD_REG + 4)
     {
@@ -1018 +1022 @@
 
 /**
+ * Handles writes to IQA_REG.
+ *
+ * @returns Strict VBox status code.
+ * @param   pDevIns     The IOMMU device instance.
+ * @param   off         The MMIO register offset.
+ * @param   cb          The size of the MMIO access (in bytes).
+ * @param   uIqaReg     The value written to IQA_REG.
+ */
+static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t off, uint64_t uIqaReg)
+{
+    /** @todo Don't allow writing this when GSTS.QIES is set? */
+
+    /* At present, we only care about the low 32-bits, high 32-bits are data. */
+    if (off == VTD_MMIO_OFF_IQA_REG)
+    {
+        PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
+        uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
+        if (fDw == VTD_IQA_REG_DW_256_BIT)
+        {
+            uint64_t const fDwMask           = VTD_BF_ECAP_REG_SMTS_MASK | VTD_BF_ECAP_REG_ADMS_MASK;
+            bool const     fSupports256BitDw = RT_BOOL(pThis->fExtCap & fDwMask);
+            if (fSupports256BitDw)
+            { /* likely */ }
+            else
+                dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_Invalid, kInvalidDescriptorWidth);
+        }
+    }
+    return VINF_SUCCESS;
+}
+
+
+/**
  * Memory access bulk (one or more 4K pages) request from a device.
  *
@@ -1111 +1147 @@
             {
                 rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
+                break;
+            }
+
+            case VTD_MMIO_OFF_IQA_REG:
+            case VTD_MMIO_OFF_IQA_REG + 4:
+            {
+                rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
                 break;
             }