Changeset 88744 in vbox
- Timestamp:
- Apr 28, 2021 11:59:02 AM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 144066
- Location:
- trunk
- Files:
-
- 2 edited
-
include/VBox/iommu-intel.h (modified) (3 diffs)
-
src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (15 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/iommu-intel.h
r88704 r88744 1517 1517 kIqei_InfoNotAvailable = 0, 1518 1518 kIqei_InvalidTailPointer, 1519 kIqei_FetchDescriptor Failed,1519 kIqei_FetchDescriptorError, 1520 1520 kIqei_InvalidDescriptorType, 1521 1521 kIqei_RsvdFieldViolation, … … 1819 1819 /** RW: Read/write mask. */ 1820 1820 #define VTD_VCRSP_REG_RW_MASK UINT64_C(0) 1821 /** @} */ 1822 1823 1824 /** @name Generic Invalidation Descriptor. 1825 * These are fields common to EVERY invalidation descriptor. 1826 * @{ */ 1827 /** Type (Lo). */ 1828 #define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0 1829 #define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f) 1830 /** R: Reserved (bits 8:4). */ 1831 #define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4 1832 #define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0) 1833 /** Type (Hi). */ 1834 #define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9 1835 #define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00) 1836 /** R: Reserved (bits 63:12). */ 1837 #define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12 1838 #define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000) 1839 RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX, 1840 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12)); 1841 1842 /** GENERIC_INV_DSC: Type. */ 1843 #define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \ 1844 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK)) 1821 1845 /** @} */ 1822 1846 … … 2155 2179 2156 2180 2181 /** @name Invalidation descriptor types. 2182 * In accordance with the Intel spec. 2183 * @{ */ 2184 #define VTD_CC_INV_DSC_TYPE 1 2185 #define VTD_IOTLB_INV_DSC_TYPE 2 2186 #define VTD_DEV_TLB_INV_DSC_TYPE 3 2187 #define VTD_IEC_INV_DSC_TYPE 4 2188 #define VTD_INV_WAIT_DSC_TYPE 5 2189 #define VTD_P_IOTLB_INV_DSC_TYPE 6 2190 #define VTD_PC_INV_DSC_TYPE 7 2191 #define VTD_P_DEV_TLB_INV_DSC_TYPE 8 2192 /** @} */ 2193 2194 2157 2195 /** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags. 2158 2196 * In accordance with the Intel spec. -
trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r88705 r88744 146 146 kDmarDiag_IqtReg_Qt_Invalid, 147 147 kDmarDiag_IqaReg_Dw_Invalid, 148 kDmarDiag_IqaReg_Dsc_Fetch_Failed, 148 kDmarDiag_IqaReg_Dsc_Fetch_Error, 149 kDmarDiag_Iqei_Dsc_Type_Invalid, 149 150 kDmarDiag_CcmdReg_Ttm_Invalid, 150 151 kDmarDiag_CcmdReg_Qi_Enabled, 151 152 kDmarDiag_CcmdReg_NotSupported, 152 /* Last member for determining array index limit. */ 153 kDmarDiag_End 153 /* Member for determining array index limit. */ 154 kDmarDiag_End, 155 /* Type size hack. */ 156 kDmarDiag_32Bit_Hack = 0x7fffffff 154 157 } DMARDIAG; 155 158 AssertCompileSize(DMARDIAG, 4); 156 159 157 /** DMAR diagnostic enum description expansion. */ 158 #define DMARDIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc 160 /** DMAR diagnostic enum description expansion. 161 * The below construct ensures typos in the input to this macro are caught 162 * during compile time. */ 163 #define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored" 159 164 160 165 /** DMAR diagnostics description. */ 161 166 static const char *const g_apszDmarDiagDesc[] = 162 167 { 163 DMARDIAG_DESC(kNone , "None" ), 164 DMARDIAG_DESC(kDmarDiag_IqtReg_Qt_NotAligned , "IqtReg_Qt_NotAligned" ), 165 DMARDIAG_DESC(kDmarDiag_IqtReg_Qt_Invalid , "IqtReg_Qt_Invalid" ), 166 DMARDIAG_DESC(kDmarDiag_IqaReg_Dw_Invalid , "IqaReg_Dw_Invalid" ), 167 DMARDIAG_DESC(kDmarDiag_IqaReg_Dsc_Fetch_Failed, "IqaReg_Dsc_Fetch_Failed"), 168 DMARDIAG_DESC(kDmarDiag_CcmdReg_Ttm_Invalid , "CcmdReg_Ttm_Invalid" ), 169 DMARDIAG_DESC(kDmarDiag_CcmdReg_Qi_Enabled , "CcmdReg_Qi_Enabled" ), 170 DMARDIAG_DESC(kDmarDiag_CcmdReg_NotSupported , "CcmdReg_NotSupported" ) 168 DMARDIAG_DESC(None ), 169 DMARDIAG_DESC(IqtReg_Qt_NotAligned ), 170 DMARDIAG_DESC(IqtReg_Qt_Invalid ), 171 DMARDIAG_DESC(IqaReg_Dw_Invalid ), 172 DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error), 173 DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ), 174 DMARDIAG_DESC(CcmdReg_Ttm_Invalid ), 175 DMARDIAG_DESC(CcmdReg_Qi_Enabled ), 176 DMARDIAG_DESC(CcmdReg_NotSupported ) 171 177 /* kDmarDiag_End */ 172 178 }; … … 188 194 /** Registers (group 1). */ 189 195 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE]; 196 197 /** @name Lazily activated registers. 198 * These are the active values for lazily activated registers. Software is free to 199 * modify the actual register values while remapping/translation is enabled but they 200 * take effect only when explicitly signaled by software, hence we need to hold the 201 * active values separately. 202 * @{ */ 203 /** Currently active IRTA_REG. */ 204 uint64_t uIrtaReg; 205 /** Currently active RTADDR_REG. */ 206 uint64_t uRtaReg; 207 /** @} */ 190 208 191 209 /** @name Register copies for a tiny bit faster and more convenient access. … … 661 679 * Reads a 32-bit register with exactly the value it contains. 662 680 * 681 * @returns The raw register value. 663 682 * @param pThis The shared DMAR device state. 664 683 * @param offReg The MMIO offset of the register. … … 676 695 * Reads a 64-bit register with exactly the value it contains. 677 696 * 697 * @returns The raw register value. 678 698 * @param pThis The shared DMAR device state. 679 699 * @param offReg The MMIO offset of the register. 680 700 */ 681 static uint 32_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)701 static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg) 682 702 { 683 703 uint8_t idxGroup; … … 793 813 * Reads a 32-bit register as it would be when read by software. 794 814 * 795 * @returns The 32-bitregister value.815 * @returns The register value. 796 816 * @param pThis The shared DMAR device state. 797 817 * @param offReg The MMIO offset of the register. … … 806 826 * Reads a 64-bit register as it would be when read by software. 807 827 * 808 * @returns The 64-bitregister value.828 * @returns The register value. 809 829 * @param pThis The shared DMAR device state. 810 830 * @param offReg The MMIO offset of the register. … … 1077 1097 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG); 1078 1098 uint32_t const fChanged = uGstsReg ^ uGcmdReg; 1079 1080 Assert(pThis->fExtCap & VTD_BF_ECAP_REG_QI_MASK); 1081 if (fChanged & VTD_BF_GCMD_REG_QIE_MASK) 1099 uint64_t const fExtCap = pThis->fExtCap; 1100 1101 /* 1102 * Queued-invalidation. 1103 */ 1104 if ( (fExtCap & VTD_BF_ECAP_REG_QI_MASK) 1105 && (fChanged & VTD_BF_GCMD_REG_QIE_MASK)) 1082 1106 { 1083 1107 if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK) … … 1093 1117 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0); 1094 1118 } 1119 } 1120 1121 /* 1122 * Set interrupt remapping table pointer. 1123 */ 1124 if ( (fExtCap & VTD_BF_ECAP_REG_IR_MASK) 1125 && (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)) 1126 { 1127 pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG); 1128 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask */, VTD_BF_GSTS_REG_IRTPS_MASK /* fOrMask */); 1095 1129 } 1096 1130 … … 1329 1363 1330 1364 DMAR_UNLOCK(pDevIns, pThisCC); 1331 LogFlowFunc(("offReg=%#x rc=%Rrc\n", offReg, VBOXSTRICTRC_VAL(rcStrict)));1365 LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict))); 1332 1366 return rcStrict; 1333 1367 } … … 1376 1410 #ifdef IN_RING3 1377 1411 /** 1412 * Process requests in the invalidation queue. 1413 * 1414 * @param pDevIns The IOMMU device instance. 1415 * @param pvRequests The requests data. 1416 * @param cbRequests The size of all requests (in bytes). 1417 * @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or 1418 * VTD_IQA_REG_DW_256_BIT). 1419 */ 1420 static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw) 1421 { 1422 uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16; 1423 for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc) 1424 { 1425 uint64_t const *puDscQwords = (uint64_t const *)((uintptr_t)pvRequests + offDsc); 1426 uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(puDscQwords[0]); 1427 switch (fDscType) 1428 { 1429 case VTD_CC_INV_DSC_TYPE: LogRelMax(32, ("%s: CC\n", DMAR_LOG_PFX)); break; 1430 case VTD_IOTLB_INV_DSC_TYPE: LogRelMax(32, ("%s: IOTLB\n", DMAR_LOG_PFX)); break; 1431 case VTD_DEV_TLB_INV_DSC_TYPE: LogRelMax(32, ("%s: DEV_TLB\n", DMAR_LOG_PFX)); break; 1432 case VTD_IEC_INV_DSC_TYPE: LogRelMax(32, ("%s: IEC_INV\n", DMAR_LOG_PFX)); break; 1433 case VTD_INV_WAIT_DSC_TYPE: LogRelMax(32, ("%s: INV_WAIT\n", DMAR_LOG_PFX)); break; 1434 case VTD_P_IOTLB_INV_DSC_TYPE: LogRelMax(32, ("%s: P_IOTLB\n", DMAR_LOG_PFX)); break; 1435 case VTD_PC_INV_DSC_TYPE: LogRelMax(32, ("%s: PC_INV\n", DMAR_LOG_PFX)); break; 1436 case VTD_P_DEV_TLB_INV_DSC_TYPE: LogRelMax(32, ("%s: P_DEVL_TLB\n", DMAR_LOG_PFX)); break; 1437 { 1438 break; 1439 } 1440 1441 default: 1442 { 1443 LogFunc(("Invalid descriptor type: %#x\n", fDscType)); 1444 dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType); 1445 return; 1446 } 1447 } 1448 } 1449 } 1450 1451 1452 1453 /** 1378 1454 * The invalidation-queue thread. 1379 1455 * … … 1390 1466 return VINF_SUCCESS; 1391 1467 1392 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK; 1393 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT; 1394 void *pvQueue = RTMemAllocZ(cbMaxQs); 1395 AssertPtrReturn(pvQueue, VERR_NO_MEMORY); 1468 /* 1469 * Pre-allocate the maximum size of the invalidation queue allowed by the spec. 1470 * This prevents trashing the heap as well as deal with out-of-memory situations 1471 * up-front while starting the VM. It also simplifies the code from having to 1472 * dynamically grow/shrink the allocation based on how software sizes the queue. 1473 * Guests normally don't alter the queue size all the time, but that's not an 1474 * assumption we can make. 1475 */ 1476 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK; 1477 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT; 1478 void *pvRequests = RTMemAllocZ(cbMaxQs); 1479 AssertPtrReturn(pvRequests, VERR_NO_MEMORY); 1396 1480 1397 1481 while (pThread->enmState == PDMTHREADSTATE_RUNNING) … … 1421 1505 if (!fIsEmpty) 1422 1506 { 1423 uint64_t const uIqaReg = dmarRegRead64(pThis, VTD_MMIO_OFF_IQA_REG); 1507 /** @todo Handle RTADDR_REG MMIO write first, for handling kIqei_InvalidTtm. I 1508 * don't think it needs to be checked/handled here? */ 1509 1510 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG); 1424 1511 uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK); 1425 1512 uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT; 1513 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW); 1514 1515 /* Paranoia. */ 1516 Assert(cbQueue <= cbMaxQs); 1517 Assert(!(offQueueTail & ~VTD_IQT_REG_RW_MASK)); 1518 Assert(!(offQueueHead & ~VTD_IQH_REG_RW_MASK)); 1519 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4))); 1520 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4))); 1521 1426 1522 if (offQueueTail <= cbQueue) 1427 1523 { 1428 Assert(offQueueTail > offQueueHead); 1429 uint32_t const cbDescriptors = offQueueTail - offQueueHead; 1430 RTGCPHYS const GCPhysQueueBase = uIqaReg & VTD_BF_IQA_REG_IQA_MASK; 1431 1524 RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead; 1525 1526 /* Don't hold the lock while reading (potentially large amount of) requests. */ 1432 1527 DMAR_UNLOCK(pDevIns, pThisR3); 1433 int rc = PDMDevHlpPhysRead(pDevIns, GCPhysQueueBase, pvQueue, cbDescriptors); 1528 1529 int rc; 1530 uint32_t cbRequests; 1531 if (offQueueTail > offQueueHead) 1532 { 1533 /* The requests have not wrapped around, read them in one go. */ 1534 cbRequests = offQueueTail - offQueueHead; 1535 rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbRequests); 1536 } 1537 else 1538 { 1539 /* The requests have wrapped around, read forward and wrapped-around. */ 1540 uint32_t const cbForward = cbQueue - offQueueHead; 1541 rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbForward); 1542 1543 uint32_t const cbWrapped = offQueueTail; 1544 if ( RT_SUCCESS(rc) 1545 && cbWrapped > 0) 1546 { 1547 rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests + cbForward, 1548 (void *)((uintptr_t)pvRequests + cbForward), cbWrapped); 1549 } 1550 cbRequests = cbForward + cbWrapped; 1551 } 1552 1553 /* Re-acquire the lock since we need to update device state. */ 1434 1554 DMAR_LOCK(pDevIns, pThisR3); 1435 1555 1436 1556 if (RT_SUCCESS(rc)) 1437 1557 { 1438 /** @todo Handle RTADDR_REG MMIO write first, for handling kIqei_InvalidTtm. I 1439 * don't think it needs to be checked/handled here? */ 1440 /** @todo Process invalidation descriptors. */ 1558 /* Indicate to software we've fetched all requests. */ 1559 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail); 1560 1561 /* Process all requests (in FIFO order) after more paranoid checks. */ 1562 Assert(cbRequests <= cbQueue); 1563 dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw); 1441 1564 } 1442 1565 else 1443 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_ Failed, kIqei_FetchDescriptorFailed);1566 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError); 1444 1567 } 1445 1568 else … … 1450 1573 } 1451 1574 1452 RTMemFree(pv Queue);1453 pv Queue= NULL;1575 RTMemFree(pvRequests); 1576 pvRequests = NULL; 1454 1577 1455 1578 LogFlowFunc(("Invalidation-queue thread terminating\n")); … … 1483 1606 { 1484 1607 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 1608 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3); 1485 1609 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; 1486 1610 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); … … 1488 1612 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0; 1489 1613 1490 DMARDIAG const enmDiag = pThis->enmDiag; 1491 const char *pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)"; 1492 1614 /* 1615 * We lock the device to get a consistent register state, but it is 1616 * ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers into 1617 * temporaries and release the lock ASAP. 1618 * 1619 * Order of register read and outputting according to 1620 * Intel VT-d spec. 10.4 "Register Descriptions" for no particular reason. 1621 */ 1622 DMAR_LOCK(pDevIns, pThisR3); 1623 1624 DMARDIAG const enmDiag = pThis->enmDiag; 1625 uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG); 1626 uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG); 1627 uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG); 1628 uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG); 1629 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG); 1630 uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG); 1631 uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG); 1632 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG); 1633 uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG); 1634 uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG); 1635 uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG); 1636 uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG); 1637 uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG); 1638 uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG); 1639 uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG); 1640 uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG); 1641 uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG); 1642 uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG); 1643 uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG); 1644 uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG); 1645 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG); 1646 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG); 1647 uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG); 1648 uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG); 1649 uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG); 1650 uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG); 1651 uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG); 1652 uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG); 1653 uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG); 1654 uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG); 1655 uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG); 1656 uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG); 1657 uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG); 1658 uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG); 1659 uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG); 1660 uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG); 1661 uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG); 1662 uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG); 1663 /** @todo Do other registers as required, we don't implement them for now. */ 1664 1665 DMAR_UNLOCK(pDevIns, pThisR3); 1666 1667 const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)"; 1493 1668 pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n"); 1494 pHlp->pfnPrintf(pHlp, " Diag = %u (%s)\n", enmDiag, pszDiag); 1669 pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag); 1670 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg); 1671 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg); 1672 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg); 1673 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg); 1674 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg); 1675 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg); 1676 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg); 1677 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg); 1678 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg); 1679 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg); 1680 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg); 1681 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg); 1682 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg); 1683 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg); 1684 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg); 1685 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg); 1686 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg); 1687 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg); 1688 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg); 1689 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg); 1690 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg); 1691 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg); 1692 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg); 1693 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg); 1694 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg); 1695 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg); 1696 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg); 1697 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg); 1698 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg); 1699 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg); 1700 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg); 1701 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg); 1702 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg); 1703 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg); 1704 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg); 1705 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg); 1706 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg); 1707 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg); 1495 1708 pHlp->pfnPrintf(pHlp, "\n"); 1496 1709 }
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