Changeset 88764 in vbox for trunk/src/VBox/Devices

Timestamp:

Apr 29, 2021 5:24:02 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 Off-by-one fix and other nits.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (4 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -1508 +1508 @@
                  *        don't think it needs to be checked/handled here? */
 
+                /*
+                 * Get the current queue size.
+                 */
                 uint64_t const uIqaReg     = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
                 uint8_t const  cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
@@ -1519 +1522 @@
                 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4)));
                 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4)));
-
-                if (offQueueTail <= cbQueue)
+                Assert(offQueueHead < cbQueue);
+
+                /*
+                 * Read the requests in the queue from guest memory into our buffer.
+                 */
+                if (offQueueTail < cbQueue)
                 {
                     RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
@@ -1559 +1566 @@
                         dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
 
-                        /* Process all requests (in FIFO order) after more paranoid checks. */
+                        /* Process all requests (in FIFO order). */
                         Assert(cbRequests <= cbQueue);
                         dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw);
@@ -1617 +1624 @@
      * temporaries and release the lock ASAP.
      *
-     * Order of register read and outputting according to
+     * Order of register being read and outputted is in according with the
      * Intel VT-d spec. 10.4 "Register Descriptions" for no particular reason.
      */