Changeset 89001 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

May 12, 2021 8:43:29 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 Interrupt remapping, work-in-progress.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (8 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -363 +363 @@
 /** Pointer to the const DMAR device state for the current context. */
 typedef CTX_SUFF(PDMAR) const PCDMARCC;
+
+/**
+ * Type of DMAR originated events that generate interrupts.
+ */
+typedef enum DMAREVENTTYPE
+{
+    /** Invalidation completion event. */
+    DMAREVENTTYPE_INV_COMPLETE = 0,
+    /** Fault event. */
+    DMAREVENTTYPE_FAULT
+} DMAREVENTTYPE;
 
 
@@ -1053 +1064 @@
 
 /**
+ * Raises an event on behalf of the DMAR.
+ *
+ * These are events that are generated by the DMAR itself (like faults and
+ * invalidation completion notifications).
+ *
+ * @param   pDevIns         The IOMMU device instance.
+ * @param   enmEventType    The DMAR event type.
+ *
+ * @remarks The DMAR lock must be held while calling this function.
+ */
+static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
+{
+    uint16_t offCtlReg;
+    uint32_t fIntrMaskedMask;
+    uint32_t fIntrPendingMask;
+    uint16_t offMsiAddrLoReg;
+    uint16_t offMsiAddrHiReg;
+    uint16_t offMsiDataReg;
+    switch (enmEventType)
+    {
+        case DMAREVENTTYPE_INV_COMPLETE:
+        {
+            offCtlReg        = VTD_MMIO_OFF_IECTL_REG;
+            fIntrMaskedMask  = VTD_BF_IECTL_REG_IM_MASK;
+            fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
+            offMsiAddrLoReg  = VTD_MMIO_OFF_IEADDR_REG;
+            offMsiAddrHiReg  = VTD_MMIO_OFF_IEUADDR_REG;
+            offMsiDataReg    = VTD_MMIO_OFF_IEDATA_REG;
+            break;
+        }
+
+        case DMAREVENTTYPE_FAULT:
+        {
+            offCtlReg        = VTD_MMIO_OFF_FECTL_REG;
+            fIntrMaskedMask  = VTD_BF_FECTL_REG_IM_MASK;
+            fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
+            offMsiAddrLoReg  = VTD_MMIO_OFF_FEADDR_REG;
+            offMsiAddrHiReg  = VTD_MMIO_OFF_FEUADDR_REG;
+            offMsiDataReg    = VTD_MMIO_OFF_FEDATA_REG;
+            break;
+        }
+
+        default:
+        {
+            /* Shouldn't ever happen. */
+            AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
+        }
+    }
+
+    /* Check if software has masked the interrupt. */
+    PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
+    uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
+    if (!(uCtlReg & fIntrMaskedMask))
+    {
+        /*
+         * Interrupt is unmasked, raise it.
+         *
+         * Interrupts generated by the DMAR have trigger mode and level as 0.
+         * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
+         */
+        MSIMSG Msi;
+        Msi.Addr.au32[0]         = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
+        Msi.Addr.au32[1]         = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
+        Msi.Data.u32             = dmarRegReadRaw32(pThis, offMsiDataReg);
+        Msi.Data.n.u1Level       = 0;
+        Msi.Data.n.u1TriggerMode = 0;
+
+        PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
+        pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
+
+        /* Clear interrupt pending bit. */
+        uCtlReg &= ~fIntrPendingMask;
+        dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
+    }
+    else
+    {
+        /* Interrupt is masked, set the interrupt pending bit. */
+        uCtlReg |= fIntrPendingMask;
+        dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
+    }
+}
+
+
+/**
  * Raises an interrupt in response to a fault event.
  *
@@ -1064 +1159 @@
     PDMAR    pThis   = PDMDEVINS_2_DATA(pDevIns, PDMAR);
     PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
-
     DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
 
@@ -1077 +1171 @@
     }
 #endif
-
-    uint32_t uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
-    if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
-    {
-        /* Software has unmasked the interrupt, raise it. */
-        MSIMSG Msi;
-        Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
-        Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
-        Msi.Data.u32     = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
-
-        /** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
-         *        FEADD_REG write it can't be anything else? */
-        pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
-
-        /* Clear interrupt pending bit. */
-        uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
-        dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
-    }
-    else
-    {
-        /* Interrupt is masked, set the interrupt pending bit. */
-        uFectlReg |= VTD_BF_FECTL_REG_IP_MASK;
-        dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
-    }
+    dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
 }
 
@@ -1114 +1185 @@
     PDMAR    pThis   = PDMDEVINS_2_DATA(pDevIns, PDMAR);
     PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
-
     DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
 
     uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
     if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
-    {
-        uint32_t uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
-        if (!(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
-        {
-            /* Software has unmasked the interrupt, raise it. */
-            MSIMSG Msi;
-            Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
-            Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
-            Msi.Data.u32     = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
-
-            pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
-
-            /* Clear interrupt pending bit. */
-            uIectlReg &= ~VTD_BF_IECTL_REG_IP_MASK;
-            dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
-        }
-        else
-        {
-            /* Interrupt is masked, set the interrupt pending bit. */
-            uIectlReg |= VTD_BF_IECTL_REG_IP_MASK;
-            dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
-        }
-    }
+        dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
 }
 #endif /* IN_RING3 */
@@ -1511 +1559 @@
                                              uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
 {
-    RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
+    RT_NOREF6(idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
+
+    PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
+    if (fFlags & PDMIOMMU_MEM_F_READ)
+        STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
+    else
+        STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
+
     return VERR_NOT_IMPLEMENTED;
 }
@@ -1591 +1646 @@
 static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
 {
-    Assert(VTD_MSI_ADDR_GET_INTR_FORMAT(pMsiIn->Addr.u64) == VTD_INTR_FORMAT_REMAPPABLE);
+    Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
 
     /* Validate reserved bits in the interrupt request. */
@@ -1735 +1790 @@
     {
         /* Handle compatibility format interrupts. */
-        bool const fIsRemapFormat = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
-        if (!fIsRemapFormat)
+        bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
+        if (!fIsRemappable)
         {
             STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));