Changeset 89007 in vbox for trunk

Timestamp:

May 12, 2021 9:23:03 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 Asserting level and trigger mode should be sufficient here since the R/W masks takes care of it already.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (2 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -1120 +1120 @@
         /*
          * Interrupt is unmasked, raise it.
-         *
          * Interrupts generated by the DMAR have trigger mode and level as 0.
          * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
          */
         MSIMSG Msi;
-        Msi.Addr.au32[0]         = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
-        Msi.Addr.au32[1]         = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
-        Msi.Data.u32             = dmarRegReadRaw32(pThis, offMsiDataReg);
-        Msi.Data.n.u1Level       = 0;
-        Msi.Data.n.u1TriggerMode = 0;
+        Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
+        Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
+        Msi.Data.u32     = dmarRegReadRaw32(pThis, offMsiDataReg);
+        Assert(Msi.Data.n.u1Level == 0);
+        Assert(Msi.Data.n.u1TriggerMode == 0);
 
         PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
@@ -1789 +1788 @@
     if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
     {
-        /* Handle compatibility format interrupts. */
         bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
         if (!fIsRemappable)
         {
+            /* Handle compatibility format interrupts. */
             STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));