Changeset 89029 in vbox

Timestamp:

May 13, 2021 8:26:23 AM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

144368

Message:

Intel IOMMU: bugref:9967 Handle clearing of FECTL_REG.IP bit.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (12 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -868 +868 @@
  * @param   offReg  The MMIO offset of the register.
  * @param   uReg    The 32-bit value to write.
- */
-static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
+ * @param   puPrev  Where to store the register value prior to writing.
+ */
+static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
 {
     /* Read current value from the 32-bit register. */
@@ -876 +877 @@
     uint32_t fRw1cMask;
     dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
+    *puPrev = uCurReg;
 
     uint32_t const fRoBits   = uCurReg & ~fRwMask;      /* Preserve current read-only and reserved bits. */
@@ -896 +898 @@
  * @param   offReg  The MMIO offset of the register.
  * @param   uReg    The 64-bit value to write.
- */
-static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
+ * @param   puPrev  Where to store the register value prior to writing.
+ */
+static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
 {
     /* Read current value from the 64-bit register. */
@@ -904 +907 @@
     uint64_t fRw1cMask;
     dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
+    *puPrev = uCurReg;
 
     uint64_t const fRoBits   = uCurReg & ~fRwMask;      /* Preserve current read-only and reserved bits. */
@@ -1227 +1231 @@
     {
         uFstsReg |= VTD_BF_FSTS_REG_PFO_MASK;
-        dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
+        dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
         return false;
     }
@@ -1399 +1403 @@
          *        ESRTPS is supported. */
         pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
+        dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
     }
 
@@ -1462 +1467 @@
 
 /**
+ * Handles writes to FECTL_REG.
+ *
+ * @returns Strict VBox status code.
+ * @param   pDevIns     The IOMMU device instance.
+ * @param   uFectlReg   The value written to FECTL_REG.
+ */
+static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
+{
+    /*
+     * If software unmasks the interrupt when the interrupt is pending, we must raise
+     * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
+     */
+    if (    (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
+        && ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
+        dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * Handles writes to FSTS_REG.
+ *
+ * @returns Strict VBox status code.
+ * @param   pDevIns     The IOMMU device instance.
+ * @param   uFstsReg    The value written to FSTS_REG.
+ * @param   uPrev       The value in FSTS_REG prior to writing it.
+ */
+static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
+{
+    /*
+     * If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
+     * the interrupt pending (IP) bit must be cleared.
+     *
+     * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
+     */
+    uint32_t const fChanged = uPrev ^ uFstsReg;
+    if (fChanged & (  VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK
+                    | VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_PFO_MASK))
+    {
+        PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
+        dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
+    }
+    return VINF_SUCCESS;
+}
+
+
+/**
  * Handles writes to IQT_REG.
  *
@@ -1562 +1614 @@
     /*
      * If software unmasks the interrupt when the interrupt is pending, we must raise
-     * the interrupt now (which will consequently clear the interrupt pending bit).
+     * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
      */
     if (    (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
         && ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
         dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * Handles writes to FRCD_REG (High 64-bits).
+ *
+ * @returns Strict VBox status code.
+ * @param   pDevIns     The IOMMU device instance.
+ * @param   offReg      The MMIO register offset.
+ * @param   cbReg       The size of the MMIO access (in bytes).
+ * @param   uFrcdHiReg  The value written to FRCD_REG.
+ * @param   uPrev       The value in FRCD_REG prior to writing it.
+ */
+static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
+{
+    /* We only care about responding to high 32-bits, low 32-bits are read-only. */
+    if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
+    {
+        /*
+         * If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
+         * Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
+         * has only 1 FRCD register.
+         *
+         * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
+         */
+        AssertCompile(DMAR_FRCD_REG_COUNT == 1);
+        uint64_t const fChanged = uPrev ^ uFrcdHiReg;
+        if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
+        {
+            Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK));  /* Software should only ever be able to clear this bit. */
+            PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
+            dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
+            dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
+        }
+    }
     return VINF_SUCCESS;
 }
@@ -1888 +1976 @@
         DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
 
-        uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv)
-                                             : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv);
+        uint64_t uPrev = 0;
+        uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv, &uPrev)
+                                             : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv, (uint32_t *)&uPrev);
         VBOXSTRICTRC rcStrict = VINF_SUCCESS;
         switch (off)
@@ -1906 +1995 @@
             }
 
+            case VTD_MMIO_OFF_FSTS_REG:         /* 32-bit */
+            {
+                rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
+                break;
+            }
+
+            case VTD_MMIO_OFF_FECTL_REG:        /* 32-bit */
+            {
+                rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
+                break;
+            }
+
             case VTD_MMIO_OFF_IQT_REG:          /* 64-bit */
             /*   VTD_MMIO_OFF_IQT_REG + 4: */   /* High 32-bits reserved. */
@@ -1920 +2021 @@
             }
 
-            case VTD_MMIO_OFF_ICS_REG:        /* 32-bit */
+            case VTD_MMIO_OFF_ICS_REG:          /* 32-bit */
             {
                 rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
@@ -1929 +2030 @@
             {
                 rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
+                break;
+            }
+
+            case DMAR_MMIO_OFF_FRCD_HI_REG:     /* 64-bit */
+            case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
+            {
+                rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
                 break;
             }