Changeset 89098 in vbox for trunk/src/VBox/Main

Timestamp:

May 17, 2021 1:58:09 PM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

144439

Message:

Intel IOMMU: bugref:9967 ConsoleImpl2, DevIoApic: When Main configures the PCI address of the I/O APIC to the BusAssignmentManager, pass it on to the I/O APIC device as well.
This will allow us to use different PCI addresses for AMD and Intel IOMMUs if required.

File:

• trunk/src/VBox/Main/src-client/ConsoleImpl2.cpp (modified) (6 diffs)

trunk/src/VBox/Main/src-client/ConsoleImpl2.cpp

@@ -832 +832 @@
 
     BOOL fIOAPIC;
+    uint32_t uIoApicPciAddress = NIL_PCIBDF;
     hrc = biosSettings->COMGETTER(IOAPICEnabled)(&fIOAPIC);                                 H();
 
@@ -868 +869 @@
     if (iommuType == IommuType_AMD)
     {
-#ifndef VBOX_WITH_IOMMU_AMD
+#ifdef VBOX_WITH_IOMMU_AMD
+        /*
+         * Reserve the specific PCI address of the "SB I/O APIC" when using
+         * an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
+         */
+        uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
+#else
         LogRel(("WARNING! AMD IOMMU not supported, IOMMU disabled.\n"));
         iommuType = IommuType_None;
@@ -876 +883 @@
     if (iommuType == IommuType_Intel)
     {
-#ifndef VBOX_WITH_IOMMU_INTEL
+#ifdef VBOX_WITH_IOMMU_INTEL
+        /*
+         * Reserve a unique PCI address for the I/O APIC when using
+         * an Intel IOMMU. For convenience we use the same address as
+         * we do on AMD, see @bugref{9967#c13}.
+         */
+        uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
+#else
         LogRel(("WARNING! Intel IOMMU not supported, IOMMU disabled.\n"));
         iommuType = IommuType_None;
@@ -1600 +1614 @@
                 hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst);                         H();
 
-                /*
-                 * Reserve the specific PCI address of the "SB I/O APIC" when using
-                 * an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
-                 */
-                PCIBusAddress PCIAddr = PCIBusAddress(VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC);
+                PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
                 hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg */, PCIAddr, true /*fGuestAddressRequired*/);  H();
             }
@@ -1616 +1626 @@
                 hrc = pBusMgr->assignPCIDevice("iommu-intel", pInst);                       H();
 
-                /*
-                 * Reserve a specific PCI address for the I/O APIC when using
-                 * an Intel IOMMU. For convenience we use the same address as
-                 * we do on AMD, see @bugref{9967#c13}.
-                 */
-                PCIBusAddress PCIAddr = PCIBusAddress(VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC);
+                PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
                 hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg */, PCIAddr, true /*fGuestAddressRequired*/);  H();
             }
@@ -1769 +1774 @@
                 InsertConfigInteger(pCfg,  "NumCPUs", cCpus);
                 if (iommuType == IommuType_Intel)
+                {
                     InsertConfigString(pCfg, "ChipType", "DMAR");
+                    InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
+                }
+                else if (iommuType == IommuType_AMD)
+                    InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
             }
         }