Changeset 89292 in vbox for trunk/src/VBox

Timestamp:

May 26, 2021 12:26:30 PM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 The SAGAW field is a bitmask of supported adjusted guest address width. Doesn't make sense to me why it's a bitmask but whatever.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (1 diff)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -730 +730 @@
 static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
 {
-    switch (uMgaw + 1)
-    {
-        case 39:    return 1;
-        case 48:    return 2;
-        case 57:    return 3;
-    }
-    return 0;
+    /*
+     * It doesn't make sense to me that a CPU (or IOMMU hardware) will support 5-level paging
+     * but not 4 or 3 level paging. So smaller page-table levels are always OR'ed in.
+     *
+     * The values below (57, 48, 39 bits) represents the levels of page-table walks for
+     * 4KB base page size.
+     * See Intel VT-d spec. 10.4.2 "Capability Register".
+     */
+    ++uMgaw;
+    uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) | RT_BIT(2) | RT_BIT(1)
+                         : uMgaw >= 48 ? RT_BIT(2) | RT_BIT(1)
+                         : uMgaw >= 39 ? RT_BIT(1)
+                         : 0;
+    return fSagaw;
 }