Changeset 89307 in vbox for trunk/src/VBox/Devices

Timestamp:

May 27, 2021 6:16:37 AM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

144654

Message:

Intel IOMMU: bugref:9967 Fix second-level large page support bitmask.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (2 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -1922 +1922 @@
                                         if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry))
                                         {
+
                                             return VERR_NOT_IMPLEMENTED;
                                         }
@@ -3143 +3144 @@
         uint8_t const fFl1gp   = 1;                                /* First-Level 1GB pages support. */
         uint8_t const fFl5lp   = 1;                                /* First-level 5-level paging support (PML5E). */
-        uint8_t const fSl2mp   = fSlts & 1;                        /* Second-Level 2MB pages support. */
-        uint8_t const fSl2gp   = fSlts & 1;                        /* Second-Level 1GB pages support. */
-        uint8_t const fSllps   = fSl2mp                            /* Second-Level large page Support. */
-                               | ((fSl2mp & fFl1gp) & RT_BIT(1));
+        uint8_t const fSl2mp   = 1;                                /* Second-Level 2MB pages support. */
+        uint8_t const fSl2gp   = fSl2mp & 1;                       /* Second-Level 1GB pages support. */
+        uint8_t const fSllps   = fSl2mp | (fSl2gp << 1);           /* Second-Level large page Support. */
         uint8_t const fMamv    = (fSl2gp ? X86_PAGE_1G_SHIFT       /* Maximum address mask value (for 2nd-level invalidations). */
                                          : X86_PAGE_2M_SHIFT)