VirtualBox

Changeset 8943 in vbox for trunk


Ignore:
Timestamp:
May 20, 2008 9:15:53 AM (17 years ago)
Author:
vboxsync
Message:

AMD-V: flush TLB when the flush count for the cpu has changed
AMD-V: Some preparational work for nested paging.

Location:
trunk
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/hwacc_svm.h

    r8940 r8943  
    248248/** MWAIT instruction when armed. */
    249249#define SVM_EXIT_MWAIT_ARMED            0x8C
    250 /** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
     250/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
    251251#define SVM_EXIT_NPF                    0x400
    252252
    … …  
    499499#pragma pack()
    500500
     501/**
     502 * SVM nested paging structure
     503 */
     504#pragma pack(1)
     505typedef union
     506{
     507    struct
     508    {
     509        uint32_t    u1NestedPaging : 1;             /* enabled/disabled */
     510    } n;
     511    uint64_t    au64[1];
     512} SVM_NPCTRL;
     513#pragma pack()
    501514
    502515/**
    … …  
    546559        SVM_EVENT   ExitIntInfo;
    547560        /** Offset 0x90 - Nested Paging. */
    548         uint64_t    u64NestedPaging;
     561        SVM_NPCTRL  NestedPaging;
    549562        /** Offset 0x98-0xA7 - Reserved. */
    550563        uint8_t     u8Reserved2[0xA8-0x98];

  • trunk/src/VBox/VMM/HWACCM.cpp

    r8876 r8943  
    470470            LogRel(("HWACCM: SVM features                      = %X\n", pVM->hwaccm.s.svm.u32Features));
    471471
     472            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
     473                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
     474            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
     475                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
     476            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
     477                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
     478            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
     479                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
     480            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
     481                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
     482
    472483            /* Only try once. */
    473484            pVM->hwaccm.s.fInitialized = true;

  • trunk/src/VBox/VMM/HWACCMInternal.h

    r8878 r8943  
    214214        /** Set if we need to flush the TLB during the world switch. */
    215215        bool                        fForceTLBFlush;
     216        /** Set if nested paging is enabled. */
     217        bool                        fNestedPaging;
    216218
    217219        /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
    218220        RTCPUID                     idLastCpu;
     221
     222        /* TLB flush count */
     223        uint32_t                    cTLBFlushes;
    219224
    220225        /** R0 memory object for the VM control block (VMCB). */
    … …  
    338343    /* Current ASID (AMD-V only) */
    339344    uint32_t    uCurrentASID;
     345    /* TLB flush count */
     346    uint32_t    cTLBFlushes;
    340347
    341348    bool        fVMXConfigured;

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r8941 r8943  
    7878
    7979    pCpu->uCurrentASID = 0;   /* we'll aways increment this the first time (host uses ASID 0) */
     80    pCpu->cTLBFlushes  = 0;
    8081    return VINF_SUCCESS;
    8182}
    … …  
    269270     */
    270271
    271     /** @todo nested paging */
    272272    pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
     273    if (pVM->hwaccm.s.svm.fNestedPaging)
     274        pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14);   /* no longer need to intercept pagefaults. */
    273275
    274276    pVMCB->ctrl.u32InterceptCtrl1 =   SVM_CTRL1_INTERCEPT_INTR
    … …  
    311313    pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
    312314
    313     /* Enable nested paging. */
    314     /** @todo how to detect support for this?? */
    315     pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
    316 
    317315    /* No LBR virtualization. */
    318316    pVMCB->ctrl.u64LBRVirt      = 0;
    … …  
    790788    STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
    791789
     790    /* Enable nested paging (disabled each time after #VMEXIT). */
     791    pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.svm.fNestedPaging;
     792
     793    /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
    792794    if (!pVM->hwaccm.s.svm.fResumeVM)
    793795    {
    794         if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
     796        if (    pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
     797                /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
     798            ||  pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
    795799        {
    796800            /* Force a TLB flush on VM entry. */
    … …  
    800804    }
    801805
    802     /* Make sure we flush the TLB when required. */
     806    /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
    803807    if (    pVM->hwaccm.s.svm.fForceTLBFlush
    804808        && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
    … …  
    808812            pCpu->uCurrentASID               = 1;       /* start at 1; host uses 0 */
    809813            pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;       /* wrap around; flush TLB */
     814            pCpu->cTLBFlushes++;
    810815        }
    811816        else
    812817            STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
     818
     819        pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
    813820    }
    814821    else
    … …  
    844851    Assert(pVMCB->ctrl.u64IOPMPhysAddr  == pVM->hwaccm.s.svm.pIOBitmapPhys);
    845852    Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
    846     Assert(pVMCB->ctrl.u64NestedPaging == 0);
    847853    Assert(pVMCB->ctrl.u64LBRVirt == 0);
    848854
    … …  
    902908        Log(("ctrl.ExitIntInfo.u1Valid          %x\n",      pVMCB->ctrl.ExitIntInfo.n.u1Valid));
    903909        Log(("ctrl.ExitIntInfo.u32ErrorCode     %x\n",      pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
    904         Log(("ctrl.u64NestedPaging              %VX64\n",   pVMCB->ctrl.u64NestedPaging));
     910        Log(("ctrl.NestedPaging                 %VX64\n",   pVMCB->ctrl.NestedPaging.au64));
    905911        Log(("ctrl.EventInject.u8Vector         %x\n",      pVMCB->ctrl.EventInject.n.u8Vector));
    906912        Log(("ctrl.EventInject.u3Type           %x\n",      pVMCB->ctrl.EventInject.n.u3Type));
    … …  
    11011107            uint32_t    errCode        = pVMCB->ctrl.u64ExitInfo1;     /* EXITINFO1 = error code */
    11021108            RTGCUINTPTR uFaultAddress  = pVMCB->ctrl.u64ExitInfo2;     /* EXITINFO2 = fault address */
     1109
     1110            Assert(!pVM->hwaccm.s.svm.fNestedPaging);
    11031111
    11041112            Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
    … …  
    12321240    }
    12331241
     1242    case SVM_EXIT_NPF:
     1243        /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
     1244        Assert(pVM->hwaccm.s.svm.fNestedPaging);
     1245        break;
     1246
    12341247    case SVM_EXIT_VINTR:
    12351248        /* A virtual interrupt is about to be delivered, which means IF=1. */
    … …  
    15751588    case SVM_EXIT_MWAIT_ARMED:
    15761589    case SVM_EXIT_MSR:
    1577     case SVM_EXIT_TASK_SWITCH:  /* can change CR3; emulate */
     1590    case SVM_EXIT_TASK_SWITCH:          /* can change CR3; emulate */
    15781591        rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
    1579         break;
    1580 
    1581     case SVM_EXIT_NPF:
    1582         AssertFailed(); /* unexpected */
    15831592        break;
    15841593
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