Changeset 8943 in vbox for trunk/src/VBox/VMM

Timestamp:

May 20, 2008 9:15:53 AM (17 years ago)

Author:

vboxsync

Message:

AMD-V: flush TLB when the flush count for the cpu has changed
AMD-V: Some preparational work for nested paging.

Location:

trunk/src/VBox/VMM

Files:

• HWACCM.cpp (modified) (1 diff)
• HWACCMInternal.h (modified) (2 diffs)
• VMMR0/HWSVMR0.cpp (modified) (11 diffs)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -470 +470 @@
             LogRel(("HWACCM: SVM features                      = %X\n", pVM->hwaccm.s.svm.u32Features));
 
+            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
+                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
+            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
+                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
+            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
+                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
+            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
+                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
+            if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
+                LogRel(("HWACCM:    AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
+
             /* Only try once. */
             pVM->hwaccm.s.fInitialized = true;

trunk/src/VBox/VMM/HWACCMInternal.h

@@ -214 +214 @@
         /** Set if we need to flush the TLB during the world switch. */
         bool                        fForceTLBFlush;
+        /** Set if nested paging is enabled. */
+        bool                        fNestedPaging;
 
         /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
         RTCPUID                     idLastCpu;
+
+        /* TLB flush count */
+        uint32_t                    cTLBFlushes;
 
         /** R0 memory object for the VM control block (VMCB). */
@@ -338 +343 @@
     /* Current ASID (AMD-V only) */
     uint32_t    uCurrentASID;
+    /* TLB flush count */
+    uint32_t    cTLBFlushes;
 
     bool        fVMXConfigured;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -78 +78 @@
 
     pCpu->uCurrentASID = 0;   /* we'll aways increment this the first time (host uses ASID 0) */
+    pCpu->cTLBFlushes  = 0;
     return VINF_SUCCESS;
 }
@@ -269 +270 @@
      */
 
-    /** @todo nested paging */
     pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
+    if (pVM->hwaccm.s.svm.fNestedPaging)
+        pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14);   /* no longer need to intercept pagefaults. */
 
     pVMCB->ctrl.u32InterceptCtrl1 =   SVM_CTRL1_INTERCEPT_INTR
@@ -311 +313 @@
     pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
 
-    /* Enable nested paging. */
-    /** @todo how to detect support for this?? */
-    pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
-
     /* No LBR virtualization. */
     pVMCB->ctrl.u64LBRVirt      = 0;
@@ -790 +788 @@
     STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
 
+    /* Enable nested paging (disabled each time after #VMEXIT). */
+    pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.svm.fNestedPaging;
+
+    /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
     if (!pVM->hwaccm.s.svm.fResumeVM)
     {
-        if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
+        if (    pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
+                /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
+            ||  pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
         {
             /* Force a TLB flush on VM entry. */
@@ -800 +804 @@
     }
 
-    /* Make sure we flush the TLB when required. */
+    /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
     if (    pVM->hwaccm.s.svm.fForceTLBFlush
         && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
@@ -808 +812 @@
             pCpu->uCurrentASID               = 1;       /* start at 1; host uses 0 */
             pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;       /* wrap around; flush TLB */
+            pCpu->cTLBFlushes++;
         }
         else
             STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
+
+        pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
     }
     else
@@ -844 +851 @@
     Assert(pVMCB->ctrl.u64IOPMPhysAddr  == pVM->hwaccm.s.svm.pIOBitmapPhys);
     Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
-    Assert(pVMCB->ctrl.u64NestedPaging == 0);
     Assert(pVMCB->ctrl.u64LBRVirt == 0);
 
@@ -902 +908 @@
         Log(("ctrl.ExitIntInfo.u1Valid          %x\n",      pVMCB->ctrl.ExitIntInfo.n.u1Valid));
         Log(("ctrl.ExitIntInfo.u32ErrorCode     %x\n",      pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
-        Log(("ctrl.u64NestedPaging              %VX64\n",   pVMCB->ctrl.u64NestedPaging));
+        Log(("ctrl.NestedPaging                 %VX64\n",   pVMCB->ctrl.NestedPaging.au64));
         Log(("ctrl.EventInject.u8Vector         %x\n",      pVMCB->ctrl.EventInject.n.u8Vector));
         Log(("ctrl.EventInject.u3Type           %x\n",      pVMCB->ctrl.EventInject.n.u3Type));
@@ -1101 +1107 @@
             uint32_t    errCode        = pVMCB->ctrl.u64ExitInfo1;     /* EXITINFO1 = error code */
             RTGCUINTPTR uFaultAddress  = pVMCB->ctrl.u64ExitInfo2;     /* EXITINFO2 = fault address */
+
+            Assert(!pVM->hwaccm.s.svm.fNestedPaging);
 
             Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
@@ -1232 +1240 @@
     }
 
+    case SVM_EXIT_NPF:
+        /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
+        Assert(pVM->hwaccm.s.svm.fNestedPaging);
+        break;
+
     case SVM_EXIT_VINTR:
         /* A virtual interrupt is about to be delivered, which means IF=1. */
@@ -1575 +1588 @@
     case SVM_EXIT_MWAIT_ARMED:
     case SVM_EXIT_MSR:
-    case SVM_EXIT_TASK_SWITCH:  /* can change CR3; emulate */
+    case SVM_EXIT_TASK_SWITCH:          /* can change CR3; emulate */
         rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
-        break;
-
-    case SVM_EXIT_NPF:
-        AssertFailed(); /* unexpected */
         break;