Changeset 89452 in vbox for trunk/src/VBox/Devices

Timestamp:

Jun 2, 2021 7:46:32 AM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

144806

Message:

Intel IOMMU: bugref:9967 Address translation, WIP.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (7 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -192 +192 @@
     kDmarDiag_Atf_Lgn_1_2,
     kDmarDiag_Atf_Lgn_1_3,
+    kDmarDiag_Atf_Lgn_4,
     kDmarDiag_Atf_Lrt_1,
     kDmarDiag_Atf_Lrt_2,
@@ -202 +203 @@
     kDmarDiag_Atf_Rta_1_3,
     kDmarDiag_Atf_Sgn_5,
+    kDmarDiag_Atf_Sgn_8,
     kDmarDiag_Atf_Ssl_1,
     kDmarDiag_Atf_Ssl_2,
@@ -269 +271 @@
     DMARDIAG_DESC(Atf_Lgn_1_2               ),
     DMARDIAG_DESC(Atf_Lgn_1_3               ),
+    DMARDIAG_DESC(Atf_Lgn_4                 ),
     DMARDIAG_DESC(Atf_Lrt_1                 ),
     DMARDIAG_DESC(Atf_Lrt_2                 ),
@@ -279 +282 @@
     DMARDIAG_DESC(Atf_Rta_1_3               ),
     DMARDIAG_DESC(Atf_Sgn_5                 ),
+    DMARDIAG_DESC(Atf_Sgn_8                 ),
     DMARDIAG_DESC(Atf_Ssl_1                 ),
     DMARDIAG_DESC(Atf_Ssl_2                 ),
@@ -1994 +1998 @@
 
 /**
+ * Validates the output address of a translation and updates the IOTLB entry for the
+ * given memory request remapping.
+ *
+ * @returns VBox status code.
+ * @param   pDevIns         The IOMMU device instance.
+ * @param   GCPhyseBase     The output address of the translation.
+ * @param   cShift          The page shift of the translation.
+ * @param   fPerm           The permissions granted for the translated.
+ * @param   idDomain        The domain ID of the translated region.
+ * @param   pMemReqRemap    The DMA memory request remapping info.
+ */
+static int dmarDrValidateAndUpdateIotlbe(PPDMDEVINS pDevIns, RTGCPHYS GCPhyseBase, uint8_t cShift, uint8_t fPerm,
+                                         uint16_t idDomain, PDMARMEMREQREMAP pMemReqRemap)
+{
+    Assert(   pMemReqRemap->fTtm == VTD_TTM_LEGACY_MODE
+           || pMemReqRemap->fTtm == VTD_TTM_SCALABLE_MODE);
+    Assert(!(GCPhyseBase & X86_PAGE_4K_OFFSET_MASK));
+
+    /* Ensure the output address is not in the interrupt address range. */
+    if (GCPhyseBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
+    {
+        pMemReqRemap->Iotlbe.GCPhysBase = GCPhyseBase;
+        pMemReqRemap->Iotlbe.cShift     = cShift;
+        pMemReqRemap->Iotlbe.fPerm      = fPerm;
+        pMemReqRemap->Iotlbe.idDomain   = idDomain;
+        return VINF_SUCCESS;
+    }
+
+    if (pMemReqRemap->fTtm == VTD_TTM_LEGACY_MODE)
+        dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lgn_4, VTDATFAULT_LGN_4, pMemReqRemap);
+    else
+        dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Sgn_8, VTDATFAULT_SGN_8, pMemReqRemap);
+    return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
+}
+
+
+/**
  * Performs second level translation.
  *
@@ -2112 +2153 @@
             if (fSllpsMask & RT_BIT(iLevel - 1))
             {
-                pMemReqRemap->Iotlbe.GCPhysBase = uPtEntity & ~(RT_BIT_64(cLevelShift) - 1);
-                pMemReqRemap->Iotlbe.cShift     = cLevelShift;
-                pMemReqRemap->Iotlbe.fPerm      = fPtPerm;
-                pMemReqRemap->Iotlbe.idDomain   = idDomain;
-                return VINF_SUCCESS;
+                RTGCPHYS const GCPhysBase = uPtEntity & ~(RT_BIT_64(cLevelShift) - 1);
+                return dmarDrValidateAndUpdateIotlbe(pDevIns, GCPhysBase, cLevelShift, fPtPerm, idDomain, pMemReqRemap);
             }
 
@@ -2131 +2169 @@
         if (iLevel == 0)
         {
-            pMemReqRemap->Iotlbe.GCPhysBase = uPtEntity & ~(RT_BIT_64(cLevelShift) - 1);
-            pMemReqRemap->Iotlbe.cShift     = cLevelShift;
-            pMemReqRemap->Iotlbe.fPerm      = fPtPerm;
-            pMemReqRemap->Iotlbe.idDomain   = idDomain;
-            return VINF_SUCCESS;
+            RTGCPHYS const GCPhysBase = uPtEntity & ~(RT_BIT_64(cLevelShift) - 1);
+            return dmarDrValidateAndUpdateIotlbe(pDevIns, GCPhysBase, cLevelShift, fPtPerm, idDomain, pMemReqRemap);
         }
     }