Changeset 8948 in vbox for trunk

Timestamp:

May 20, 2008 11:09:40 AM (17 years ago)

Author:

vboxsync

Message:

Nested paging updates

Location:

trunk

Files:

• include/VBox/hwacc_svm.h (modified) (1 diff)
• src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (7 diffs)

trunk/include/VBox/hwacc_svm.h

@@ -565 +565 @@
         SVM_EVENT   EventInject;
         /** Offset 0xB0 - Host CR3 for nested paging. */
-        uint64_t    u64HostCR3;
+        uint64_t    u64NestedPagingCR3;
         /** Offset 0xB8 - LBR Virtualization. */
         uint64_t    u64LBRVirt;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -255 +255 @@
     /* Note: CR8 reads will refer to V_TPR, so no need to catch them. */
     /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
-    pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
+    if (!pVM->hwaccm.s.svm.fNestedPaging)
+        pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
+    else    
+        pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0);
 
     /*
      * CR0/3/4 writes must be intercepted for obvious reasons.
      */
-    pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
+    if (!pVM->hwaccm.s.svm.fNestedPaging)
+        pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
+    else
+        pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(8);
 
     /* Intercept all DRx reads and writes. */
@@ -583 +589 @@
         val &= ~(X86_CR0_CD|X86_CR0_NW);
 
-        val |= X86_CR0_PG;          /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
-        val |= X86_CR0_WP;          /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
+        /* Note: WP is not relevant in nested paging mode as we catch accesses on the (host) physical level. */
+        /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation is still active. */
+        if (!pVM->hwaccm.s.svm.fNestedPaging)
+        {
+            val |= X86_CR0_PG;          /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
+            val |= X86_CR0_WP;          /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
+        }
         pVMCB->guest.u64CR0 = val;
     }
@@ -593 +604 @@
     {
         /* Save our shadow CR3 register. */
-        pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
+        if (!pVM->hwaccm.s.svm.fNestedPaging)
+            pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
+        else
+            pVMCB->guest.u64CR3 = pCtx->cr3;
     }
 
@@ -599 +613 @@
     {
         val = pCtx->cr4;
-        switch(pVM->hwaccm.s.enmShadowMode)
-        {
-        case PGMMODE_REAL:
-        case PGMMODE_PROTECTED:     /* Protected mode, no paging. */
-            AssertFailed();
-            return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
-
-        case PGMMODE_32_BIT:        /* 32-bit paging. */
-            break;
-
-        case PGMMODE_PAE:           /* PAE paging. */
-        case PGMMODE_PAE_NX:        /* PAE paging with NX enabled. */
-            /** @todo use normal 32 bits paging */
-            val |= X86_CR4_PAE;
-            break;
-
-        case PGMMODE_AMD64:         /* 64-bit AMD paging (long mode). */
-        case PGMMODE_AMD64_NX:      /* 64-bit AMD paging (long mode) with NX enabled. */
-            AssertFailed();
-            return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
-
-        default:                   /* shut up gcc */
-            AssertFailed();
-            return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
+        if (!pVM->hwaccm.s.svm.fNestedPaging)
+        {
+            switch(pVM->hwaccm.s.enmShadowMode)
+            {
+            case PGMMODE_REAL:
+            case PGMMODE_PROTECTED:     /* Protected mode, no paging. */
+                AssertFailed();
+                return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
+
+            case PGMMODE_32_BIT:        /* 32-bit paging. */
+                break;
+
+            case PGMMODE_PAE:           /* PAE paging. */
+            case PGMMODE_PAE_NX:        /* PAE paging with NX enabled. */
+                /** @todo use normal 32 bits paging */
+                val |= X86_CR4_PAE;
+                break;
+
+            case PGMMODE_AMD64:         /* 64-bit AMD paging (long mode). */
+            case PGMMODE_AMD64_NX:      /* 64-bit AMD paging (long mode) with NX enabled. */
+                AssertFailed();
+                return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
+
+            default:                   /* shut up gcc */
+                AssertFailed();
+                return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
+            }
         }
         pVMCB->guest.u64CR4 = val;
@@ -703 +720 @@
     unsigned    cResume = 0;
 
+    Assert(!pVM->hwaccm.s.svm.fNestedPaging);
+
     STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
 
@@ -788 +807 @@
     STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
 
-    /* Enable nested paging (disabled each time after #VMEXIT). */
+    /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
     pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.svm.fNestedPaging;
 
@@ -922 +941 @@
         Log(("ctrl.EventInject.u32ErrorCode     %x\n",      pVMCB->ctrl.EventInject.n.u32ErrorCode));
 
-        Log(("ctrl.u64HostCR3                   %VX64\n",   pVMCB->ctrl.u64HostCR3));
+        Log(("ctrl.u64NestedPagingCR3           %VX64\n",   pVMCB->ctrl.u64NestedPagingCR3));
         Log(("ctrl.u64LBRVirt                   %VX64\n",   pVMCB->ctrl.u64LBRVirt));