Changeset 89666 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

Jun 14, 2021 7:28:22 AM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

145112

Message:

Intel IOMMU: bugref:9967 Validate the offsets of our implementation-defined MMIO registers in saved states.

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (10 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -110 +110 @@
 /** Size of the group 0 (in bytes). */
 #define DMAR_MMIO_GROUP_0_SIZE                      (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
-/**< Implementation-specific MMIO offset of IVA_REG. */
+/** Number of MMIO register offsets defined by our implementation (for saved
+ *  states) - IVA_REG, IOTLB_REG, FRCD_LO, FRCD_HI. */
+#define DMAR_MMIO_OFF_IMPL_COUNT                    4
+/** Implementation-specific MMIO offset of IVA_REG (used in saved state). */
 #define DMAR_MMIO_OFF_IVA_REG                       0xe50
-/**< Implementation-specific MMIO offset of IOTLB_REG. */
+/** Implementation-specific MMIO offset of IOTLB_REG (used in saved state). */
 #define DMAR_MMIO_OFF_IOTLB_REG                     0xe58
-/**< Implementation-specific MMIO offset of FRCD_LO_REG. */
+/** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */
 #define DMAR_MMIO_OFF_FRCD_LO_REG                   0xe70
-/**< Implementation-specific MMIO offset of FRCD_HI_REG. */
+/** Implementation-specific MMIO offset of FRCD_HI_REG (used in saved state). */
 #define DMAR_MMIO_OFF_FRCD_HI_REG                   0xe78
 AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
@@ -3945 +3948 @@
     pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
 
+    /*
+     * Save our implemention-defined MMIO registers offsets.
+     * The register themselves are currently all part of group 1 (saved above).
+     * We save these to ensure they're located where the code expects them while loading state.
+     */
+    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT);
+    AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 4);
+    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG);
+    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IOTLB_REG);
+    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG);
+    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_HI_REG);
+
     /* Save lazily activated registers. */
     pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
@@ -3982 +3997 @@
     {
         /* VER_REG */
-        uint32_t uVerReg;
+        uint32_t uVerReg = 0;
         int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
         AssertRCReturn(rc, rc);
@@ -3989 +4004 @@
                               rcDataErr);
         /* CAP_REG */
-        uint64_t fCapReg;
+        uint64_t fCapReg = 0;
         pHlp->pfnSSMGetU64(pSSM, &fCapReg);
         AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
@@ -3995 +4010 @@
                               rcDataErr);
         /* ECAP_REG */
-        uint64_t fExtCapReg;
+        uint64_t fExtCapReg = 0;
         pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
         AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
@@ -4007 +4022 @@
     {
         /* Group count. */
-        uint32_t cRegGroups;
+        uint32_t cRegGroups = 0;
         pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
         AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
@@ -4013 +4028 @@
                                cRegGroups), rcFmtErr);
         /* Group 0. */
-        uint32_t cbRegs0;
+        uint32_t cbRegs0 = 0;
         pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
         AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
@@ -4020 +4035 @@
         pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
         /* Group 1. */
-        uint32_t cbRegs1;
+        uint32_t cbRegs1 = 0;
         pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
         AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
@@ -4026 +4041 @@
                                cbRegs1), rcFmtErr);
         pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
+    }
+
+    /*
+     * Validate implementation-defined MMIO register offsets.
+     */
+    {
+        /* Offset count. */
+        uint16_t cOffsets = 0;
+        pHlp->pfnSSMGetU16(pSSM, &cOffsets);
+        AssertLogRelMsgReturn(cOffsets == DMAR_MMIO_OFF_IMPL_COUNT,
+                              ("%s: MMIO offset count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IMPL_COUNT,
+                               cOffsets), rcFmtErr);
+        /* IVA_REG. */
+        uint16_t offReg = 0;
+        pHlp->pfnSSMGetU16(pSSM, &offReg);
+        AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IVA_REG,
+                              ("%s: IVA_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IVA_REG,
+                               offReg), rcFmtErr);
+        /* IOTLB_REG. */
+        pHlp->pfnSSMGetU16(pSSM, &offReg);
+        AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IOTLB_REG,
+                              ("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG,
+                               offReg), rcFmtErr);
+        /* FRCD_LO_REG. */
+        pHlp->pfnSSMGetU16(pSSM, &offReg);
+        AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_LO_REG,
+                              ("%s: FRCD_LO_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_LO_REG,
+                               offReg), rcFmtErr);
+        /* FRCD_HI_REG. */
+        pHlp->pfnSSMGetU16(pSSM, &offReg);
+        AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_HI_REG,
+                              ("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG,
+                               offReg), rcFmtErr);
     }
 
@@ -4046 +4094 @@
      */
     {
-        uint32_t uEndMarker;
+        uint32_t uEndMarker = 0;
         int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
         AssertRCReturn(rc, rc);