Changeset 89726 in vbox for trunk/src/VBox
- Timestamp:
- Jun 16, 2021 5:23:55 AM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 145177
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r89668 r89726 364 364 /** Maximum guest-address width (MGAW) invalid address mask. */ 365 365 uint64_t fMgawInvMask; 366 /** Context-entry qword-1 valid mask. */ 367 uint64_t fCtxEntryQw1ValidMask; 366 368 /** Maximum supported paging level (3, 4 or 5). */ 367 369 uint8_t cMaxPagingLevel; … … 1402 1404 static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns) 1403 1405 { 1404 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);1405 1406 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC); 1406 1407 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC); … … 1408 1409 #ifdef RT_STRICT 1409 1410 { 1411 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 1410 1412 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG); 1411 1413 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK … … 2445 2447 { 2446 2448 /* Validate reserved bits in the context-entry. */ 2449 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR); 2447 2450 if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK) 2448 && !(uCtxEntryQword1 & ~ VTD_CONTEXT_ENTRY_1_VALID_MASK))2451 && !(uCtxEntryQword1 & ~pThis->fCtxEntryQw1ValidMask)) 2449 2452 { 2450 2453 /* Get the domain ID for this mapping. */ … … 2452 2455 2453 2456 /* Validate the translation type (TT). */ 2454 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);2455 2457 uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT); 2456 2458 switch (fTt) … … 2476 2478 return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap); 2477 2479 } 2478 else 2479 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux); 2480 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux); 2480 2481 } 2481 2482 else … … 2562 2563 static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap) 2563 2564 { 2564 RT_NOREF2(uRtaddrReg, pMemReqRemap); 2565 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 2566 Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK); 2565 RT_NOREF3(pDevIns, uRtaddrReg, pMemReqRemap); 2567 2566 return VERR_NOT_IMPLEMENTED; 2568 2567 } … … 3832 3831 uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */ 3833 3832 uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */ 3834 AssertCompile(DMAR_ND <= 6);3835 3833 3836 3834 pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd) … … 3857 3855 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg); 3858 3856 3859 pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK; 3860 pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits; 3861 pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw); 3857 AssertCompile(fNd <= RT_ELEMENTS(g_auNdMask)); 3858 pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK; 3859 pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits; 3860 pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw); 3861 pThis->fCtxEntryQw1ValidMask = VTD_BF_1_CONTEXT_ENTRY_AW_MASK 3862 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK 3863 | RT_BF_MAKE(VTD_BF_1_CONTEXT_ENTRY_DID, g_auNdMask[fNd]); 3862 3864 } 3863 3865
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