Changeset 8974 in vbox for trunk/src/VBox

Timestamp:

May 20, 2008 6:57:52 PM (17 years ago)

Author:

vboxsync

Message:

INC & DEC

Location:

trunk/src/VBox/Disassembler/testcase

Files:

• tstAsmLock-1.asm (modified) (1 diff)
• tstAsmLock-2.asm (modified) (1 diff)

trunk/src/VBox/Disassembler/testcase/tstAsmLock-1.asm

@@ -321 +321 @@
 %endif
 
+    ;
     ; DEC
+    ;
+        ; fe /1         DEC reg8/mem8 - sans reg dst
+    lock dec byte [40cc0h]
+    lock dec byte [xBX]
+    lock dec byte [xSI]
+        ; ff /1         DEC regX/memX - sans reg dst
+    lock dec word [40cc0h]
+    lock dec word [xBX]
+    lock dec word [xSI]
+    lock dec dword [40cc0h]
+    lock dec dword [xBX]
+    lock dec dword [xSI]
+%ifdef WITH_64_BIT_TESTS
+    lock dec qword [40cc0h]
+    lock dec qword [xBX]
+    lock dec qword [xSI]
+    lock dec qword [r8]
+    lock dec qword [r12]
+%endif
+
+    ;
     ; INC
+    ;
+        ; fe /0         INC reg8/mem8 - sans reg dst
+    lock inc byte [40cc0h]
+    lock inc byte [xBX]
+    lock inc byte [xSI]
+        ; ff /0         INC regX/memX - sans reg dst
+    lock inc word [40cc0h]
+    lock inc word [xBX]
+    lock inc word [xSI]
+    lock inc dword [40cc0h]
+    lock inc dword [xBX]
+    lock inc dword [xSI]
+%ifdef WITH_64_BIT_TESTS
+    lock inc qword [40cc0h]
+    lock inc qword [xBX]
+    lock inc qword [xSI]
+    lock inc qword [r8]
+    lock inc qword [r12]
+%endif
+
     ; NEG
     ; NOT

trunk/src/VBox/Disassembler/testcase/tstAsmLock-2.asm

@@ -242 +242 @@
         ; all valid.
 
+    ;
     ; DEC
+    ;
+        ; fe /1         DEC reg8/mem8 - with reg dst
+    lock dec bl
+        ; ff /1         DEC regX/memX - with reg dst
+
+%if TEST_BITS != 64     ; cannot force these two in 32 and 16 bit mode.
+    db 066h, 0f0h, 0ffh, 0cbh
+    db 0f0h, 0ffh, 0cbh
+%else
+    lock dec bx
+    lock dec ebx
+ %ifdef WITH_64_BIT_TESTS
+    lock dec rbx
+    lock dec r8
+    lock dec r14
+ %endif
+%endif
+%if TEST_BITS != 64
+        ; 48 +rw        DEC reg16
+    lock dec dx
+        ; 48 +rd        DEC reg32
+    lock dec edx
+%endif
+
+    ;
     ; INC
+    ;
+        ; fe /1         INC reg8/mem8 - with reg dst
+    lock inc bl
+        ; ff /1         INC regX/memX - with reg dst
+
+%if TEST_BITS != 64     ; cannot force these two in 32 and 16 bit mode.
+    db 066h, 0f0h, 0ffh, 0c3h
+    db 0f0h, 0ffh, 0c3h
+%else
+    lock inc bx
+    lock inc ebx
+ %ifdef WITH_64_BIT_TESTS
+    lock inc rbx
+    lock inc r8
+    lock inc r14
+ %endif
+%endif
+%if TEST_BITS != 64
+        ; 48 +rw        INC reg16
+    lock inc dx
+        ; 48 +rd        INC reg32
+    lock inc edx
+%endif
+
     ; NEG
     ; NOT