Changeset 9008 in vbox for trunk/src/VBox/VMM
- Timestamp:
- May 21, 2008 10:17:41 AM (17 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/Makefile.kmk
r8797 r9008 102 102 VMMAll/CPUMAllRegs.cpp \ 103 103 VMMAll/DBGFAll.cpp \ 104 VMMAll/HWACCMAll.cpp \ 104 105 VMMAll/IOMAll.cpp \ 105 106 VMMAll/IOMAllMMIO.cpp \ … … 390 391 VMMAll/EMAll.cpp \ 391 392 VMMAll/EMAllA.asm \ 393 VMMAll/HWACCMAll.cpp \ 392 394 VMMAll/IOMAll.cpp \ 393 395 VMMAll/IOMAllMMIO.cpp \ -
trunk/src/VBox/VMM/PGMInternal.h
r9001 r9008 268 268 # define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt)) 269 269 #elif defined(IN_RING0) 270 # define PGM_INVL_PG(GCVirt) HWACCM R0InvalidatePage(pVM, (RTGCPTR)(GCVirt))270 # define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt)) 271 271 #else 272 # define PGM_INVL_PG(GCVirt) ((void)0)272 # define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt)) 273 273 #endif 274 274 … … 281 281 # define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3() 282 282 #elif defined(IN_RING0) 283 # define PGM_INVL_BIG_PG(GCVirt) HWACCM R0FlushTLB(pVM)283 # define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM) 284 284 #else 285 # define PGM_INVL_BIG_PG(GCVirt) ((void)0)285 # define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM) 286 286 #endif 287 287 … … 292 292 # define PGM_INVL_GUEST_TLBS() ASMReloadCR3() 293 293 #elif defined(IN_RING0) 294 # define PGM_INVL_GUEST_TLBS() HWACCM R0FlushTLB(pVM)294 # define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM) 295 295 #else 296 # define PGM_INVL_GUEST_TLBS() ((void)0)296 # define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM) 297 297 #endif 298 298 -
trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp
r8155 r9008 166 166 } 167 167 pVM->pgm.s.fPhysCacheFlushPending = true; 168 HWACCMFlushTLB(pVM); 168 169 #ifndef IN_RING3 169 170 REMNotifyHandlerPhysicalRegister(pVM, enmType, GCPhys, GCPhysLast - GCPhys + 1, !!pfnHandlerR3); … … 298 299 * Clear the page bits and notify the REM about this change. 299 300 */ 301 HWACCMFlushTLB(pVM); 300 302 pgmHandlerPhysicalResetRamFlags(pVM, pCur); 301 303 pgmHandlerPhysicalDeregisterNotifyREM(pVM, pCur); … … 540 542 pCur->Core.KeyLast - GCPhys + 1, !!pCur->pfnHandlerR3, fRestoreAsRAM); 541 543 #endif 544 HWACCMFlushTLB(pVM); 542 545 pgmUnlock(pVM); 543 546 Log(("PGMHandlerPhysicalModify: GCPhysCurrent=%VGp -> GCPhys=%VGp GCPhysLast=%VGp\n", … … 631 634 632 635 /** 633 * Split ts a physical access handler in two.636 * Splits a physical access handler in two. 634 637 * 635 638 * @returns VBox status code. … … 813 816 } 814 817 pVM->pgm.s.fPhysCacheFlushPending = true; 818 HWACCMFlushTLB(pVM); 815 819 816 820 rc = VINF_SUCCESS; -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r8958 r9008 908 908 static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser) 909 909 { 910 #if def IN_RING0910 #ifndef IN_GC 911 911 const PVM pVM = pPool->CTXSUFF(pVM); 912 912 #endif … … 1035 1035 static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage) 1036 1036 { 1037 #if def IN_RING01037 #ifndef IN_GC 1038 1038 const PVM pVM = pPool->CTXSUFF(pVM); 1039 1039 #endif -
trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
r8879 r9008 812 812 return SVMR0RunGuestCode(pVM, pCtx, &HWACCMR0Globals.aCpuInfo[idCpu]); 813 813 } 814 }815 816 /**817 * Invalidates a guest page818 *819 * @returns VBox status code.820 * @param pVM The VM to operate on.821 * @param GCVirt Page to invalidate822 */823 HWACCMR0DECL(int) HWACCMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)824 {825 if (pVM->hwaccm.s.svm.fSupported)826 return SVMR0InvalidatePage(pVM, GCVirt);827 828 return VINF_SUCCESS;829 }830 831 /**832 * Flushes the guest TLB833 *834 * @returns VBox status code.835 * @param pVM The VM to operate on.836 */837 HWACCMR0DECL(int) HWACCMR0FlushTLB(PVM pVM)838 {839 if (pVM->hwaccm.s.svm.fSupported)840 return SVMR0FlushTLB(pVM);841 842 return VINF_SUCCESS;843 814 } 844 815 -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r8965 r9008 266 266 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8); 267 267 else 268 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT( 4) | RT_BIT(8);268 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(8); 269 269 270 270 /* Intercept all DRx reads and writes. */ … … 1414 1414 break; 1415 1415 case 4: 1416 Assert(!pVM->hwaccm.s.svm.fNestedPaging); 1416 1417 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4; 1417 1418 break; … … 1877 1878 } 1878 1879 1879 /**1880 * Flushes the guest TLB1881 *1882 * @returns VBox status code.1883 * @param pVM The VM to operate on.1884 */1885 HWACCMR0DECL(int) SVMR0FlushTLB(PVM pVM)1886 {1887 Log2(("SVMR0FlushTLB\n"));1888 pVM->hwaccm.s.svm.fForceTLBFlush = true;1889 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBManual);1890 return VINF_SUCCESS;1891 } -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.h
r8878 r9008 127 127 HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx); 128 128 129 /**130 * Invalidates a guest page131 *132 * @returns VBox status code.133 * @param pVM The VM to operate on.134 * @param GCVirt Page to invalidate135 */136 HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt);137 138 /**139 * Flushes the guest TLB140 *141 * @returns VBox status code.142 * @param pVM The VM to operate on.143 */144 HWACCMR0DECL(int) SVMR0FlushTLB(PVM pVM);145 146 129 147 130 /* Convert hidden selector attribute word between VMX and SVM formats. */ -
trunk/src/VBox/VMM/VMMR0/PGMR0.cpp
r9001 r9008 82 82 83 83 /* AMD uses the host's paging mode; Intel's version is on the todo list */ 84 Assert(enmShwPagingMode == PGMMODE_32_BIT || enmShwPagingMode == PGMMODE_PAE ); //|| enmShwPagingMode == PGMMODE_AMD64);84 Assert(enmShwPagingMode == PGMMODE_32_BIT || enmShwPagingMode == PGMMODE_PAE || enmShwPagingMode == PGMMODE_AMD64); 85 85 86 86 #ifdef VBOX_WITH_STATISTICS
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