Changeset 90158 in vbox
- Timestamp:
- Jul 12, 2021 1:49:57 PM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 145661
- Location:
- trunk/src/VBox/Devices/Audio
- Files:
-
- 2 edited
-
DevHda.cpp (modified) (16 diffs)
-
DevHda.h (modified) (17 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevHda.cpp
r90149 r90158 285 285 static FNHDAREGREAD hdaRegReadWALCLK; 286 286 static FNHDAREGWRITE hdaRegWriteSSYNC; 287 static FNHDAREGWRITE hdaRegWriteNewSSYNC; 287 288 static FNHDAREGWRITE hdaRegWriteCORBWP; 288 289 static FNHDAREGWRITE hdaRegWriteCORBRP; … … 299 300 /** @} */ 300 301 301 /** @name {IOB}SDn write functions.302 /** @name {IOB}SDn read/write functions. 302 303 * @{ 303 304 */ … … 311 312 static FNHDAREGWRITE hdaRegWriteSDBDPL; 312 313 static FNHDAREGWRITE hdaRegWriteSDBDPU; 314 static FNHDAREGREAD hdaRegReadSDnPIB; 315 static FNHDAREGREAD hdaRegReadSDnEFIFOS; 313 316 /** @} */ 314 317 … … 410 413 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name) 411 414 415 /** Skylake stream registers. */ 416 #define HDA_REG_MAP_SKYLAKE_STRM(a_off, a_StrPrefix) \ 417 /* offset size read mask write mask flags read callback write callback index, abbrev, description */ \ 418 /* ------- ------- ---------- ---------- -------------- -------------- ----------------- ----------------------------- ----------- */ \ 419 /* 0x1084 */ \ 420 HDA_REG_ENTRY_STR(a_off + 0x04, 0x00004, 0xffffffff, 0x00000000, HDA_RD_F_NONE, hdaRegReadSDnPIB, hdaRegWriteUnimpl, a_StrPrefix, DPIB, "DMA Position In Buffer" ), \ 421 /* 0x1094 */ \ 422 HDA_REG_ENTRY_STR(a_off + 0x14, 0x00004, 0xffffffff, 0x00000000, HDA_RD_F_NONE, hdaRegReadSDnEFIFOS, hdaRegWriteUnimpl, a_StrPrefix, EFIFOS, "Extended FIFO Size" ) 423 424 412 425 /** See 302349 p 6.2. */ 413 426 static const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] = … … 424 437 HDA_REG_ENTRY(0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, STATESTS, "State Change Status" ), 425 438 HDA_REG_ENTRY(0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , GSTS, "Global Status" ), 439 HDA_REG_ENTRY(0x00014, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , LLCH, "Linked List Capabilities Header" ), 426 440 HDA_REG_ENTRY(0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteU16 , OUTSTRMPAY, "Output Stream Payload Capability" ), 427 441 HDA_REG_ENTRY(0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , INSTRMPAY, "Input Stream Payload Capability" ), … … 429 443 HDA_REG_ENTRY(0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , INTSTS, "Interrupt Status" ), 430 444 HDA_REG_ENTRY_EX(0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , 0, "WALCLK", "Wall Clock Counter" ), 431 HDA_REG_ENTRY(0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteSSYNC , SSYNC, "Stream Synchronization" ), 445 HDA_REG_ENTRY(0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteSSYNC , SSYNC, "Stream Synchronization (old)" ), 446 HDA_REG_ENTRY(0x00038, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteNewSSYNC, SSYNC, "Stream Synchronization (new)" ), 432 447 HDA_REG_ENTRY(0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , CORBLBASE, "CORB Lower Base Address" ), 433 448 HDA_REG_ENTRY(0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , CORBUBASE, "CORB Upper Base Address" ), … … 458 473 HDA_REG_MAP_DEF_STREAM(5, SD5), 459 474 HDA_REG_MAP_DEF_STREAM(6, SD6), 460 HDA_REG_MAP_DEF_STREAM(7, SD7) 475 HDA_REG_MAP_DEF_STREAM(7, SD7), 476 HDA_REG_ENTRY(0x00c00, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , MLCH, "Multiple Links Capability Header" ), 477 HDA_REG_ENTRY(0x00c04, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , MLCD, "Multiple Links Capability Declaration" ), 478 HDA_REG_MAP_SKYLAKE_STRM(0x01080, SD0), 479 HDA_REG_MAP_SKYLAKE_STRM(0x010a0, SD1), 480 HDA_REG_MAP_SKYLAKE_STRM(0x010c0, SD2), 481 HDA_REG_MAP_SKYLAKE_STRM(0x010e0, SD3), 482 HDA_REG_MAP_SKYLAKE_STRM(0x01100, SD4), 483 HDA_REG_MAP_SKYLAKE_STRM(0x01120, SD5), 484 HDA_REG_MAP_SKYLAKE_STRM(0x01140, SD6), 485 HDA_REG_MAP_SKYLAKE_STRM(0x01160, SD7), 461 486 }; 462 487 … … 470 495 * HDA register aliases (HDA spec 3.3.45). 471 496 * @remarks Sorted by offReg. 497 * @remarks Lookup code ASSUMES this starts somewhere after g_aHdaRegMap ends. 472 498 */ 473 499 static struct HDAREGALIAS … … 721 747 if (offReg < g_aHdaRegMap[idxMiddle].off) 722 748 { 723 if (idxLow == idxMiddle) 749 if (idxLow != idxMiddle) 750 idxEnd = idxMiddle; 751 else 724 752 break; 725 idxEnd = idxMiddle;726 753 } 727 754 else if (offReg > g_aHdaRegMap[idxMiddle].off) 728 755 { 729 756 idxLow = idxMiddle + 1; 730 if (idxLow >= idxEnd) 757 if (idxLow < idxEnd) 758 { /* likely */ } 759 else 731 760 break; 732 761 } … … 1343 1372 } 1344 1373 1345 static VBOXSTRICTRC hdaRegWriteSSYNC(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value) 1346 { 1374 static VBOXSTRICTRC hdaRegWriteSSYNCWorker(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, const char *pszCaller) 1375 { 1376 RT_NOREF(pszCaller); 1377 1347 1378 /* 1348 1379 * The SSYNC register is a DMA pause mask where each bit represents a stream. … … 1363 1394 { 1364 1395 #if 0 /** @todo implement SSYNC: ndef IN_RING3 */ 1365 RT_NOREF(pDevIns); 1366 Log3Func(("Going to ring-3 to handle SSYNC change: %#x\n", fChanged)); 1396 Log3(("%s: Going to ring-3 to handle SSYNC change: %#x\n", pszCaller, fChanged)); 1367 1397 return VINF_IOM_R3_MMIO_WRITE; 1368 1398 #else … … 1372 1402 else if (fNew & fMask) 1373 1403 { 1374 Log3 Func(("SSYNC bit %u set\n", i));1404 Log3(("%Rfn: SSYNC bit %u set\n", pszCaller, i)); 1375 1405 /* See code in SDCTL around hdaR3StreamTimerMain call. */ 1376 1406 } 1377 1407 else 1378 1408 { 1379 Log3 Func(("SSYNC bit %u cleared\n", i));1409 Log3(("%Rfn: SSYNC bit %u cleared\n", pszCaller, i)); 1380 1410 /* The next DMA timer callout will not do anything. */ 1381 1411 } 1382 RT_NOREF(pDevIns);1383 1412 #endif 1384 1413 } … … 1386 1415 HDA_REG(pThis, SSYNC) = fNew; 1387 1416 return VINF_SUCCESS; 1417 } 1418 1419 static VBOXSTRICTRC hdaRegWriteSSYNC(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value) 1420 { 1421 RT_NOREF(pDevIns); 1422 return hdaRegWriteSSYNCWorker(pThis, iReg, u32Value, __FUNCTION__); 1423 } 1424 1425 static VBOXSTRICTRC hdaRegWriteNewSSYNC(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value) 1426 { 1427 RT_NOREF(pDevIns); 1428 return hdaRegWriteSSYNCWorker(pThis, iReg, u32Value, __FUNCTION__); 1388 1429 } 1389 1430 … … 2129 2170 return hdaRegWriteSDBDPX(pDevIns, pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg)); 2130 2171 } 2172 2173 /** Skylake specific. */ 2174 static VBOXSTRICTRC hdaRegReadSDnPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value) 2175 { 2176 uint8_t const uSD = HDA_SD_NUM_FROM_SKYLAKE_REG(DPIB, iReg); 2177 LogFlowFunc(("uSD=%u -> SDnLPIB\n", uSD)); 2178 return hdaRegReadLPIB(pDevIns, pThis, HDA_SD_TO_REG(LPIB, uSD), pu32Value); 2179 } 2180 2181 /** Skylake specific. */ 2182 static VBOXSTRICTRC hdaRegReadSDnEFIFOS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value) 2183 { 2184 /** @todo This is not implemented as I have found no specs yet. */ 2185 RT_NOREF(pDevIns, pThis, iReg); 2186 LogFunc(("TODO - need register spec: uSD=%u\n", HDA_SD_NUM_FROM_SKYLAKE_REG(DPIB, iReg))); 2187 *pu32Value = 256; 2188 return VINF_SUCCESS; 2189 } 2190 2131 2191 2132 2192 static VBOXSTRICTRC hdaRegReadIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value) … … 2920 2980 * RIRB response -- so initialize RINTCNT to 1 by default. */ 2921 2981 HDA_REG(pThis, RINTCNT) = 0x1; 2982 /* For newer devices, there is a capability list offset word at 0x14, linux read it, does 2983 no checking and simply reads the dword it specifies. The list terminates when the lower 2984 16 bits are zero. See snd_hdac_bus_parse_capabilities. Table 5-2 in intel 341081-002 2985 specifies this to be 0xc00 and chaining with 0x800, 0x500 and 0x1f00. We just terminate 2986 it at 0xc00 for now. */ 2987 HDA_REG(pThis, LLCH) = 0xc00; 2988 HDA_REG(pThis, MLCH) = 0x0; 2989 HDA_REG(pThis, MLCD) = 0x0; 2922 2990 2923 2991 /* … … 5144 5212 ("[%#x] = {%#x LB %#x}\n", i, pReg->off, pReg->cb)); 5145 5213 } 5146 5214 Assert(strcmp(g_aHdaRegMap[HDA_REG_SSYNC].pszName, "SSYNC") == 0); 5215 Assert(strcmp(g_aHdaRegMap[HDA_REG_DPUBASE].pszName, "DPUBASE") == 0); 5216 Assert(strcmp(g_aHdaRegMap[HDA_REG_MLCH].pszName, "MLCH") == 0); 5217 Assert(strcmp(g_aHdaRegMap[HDA_REG_SD3DPIB].pszName, "SD3DPIB") == 0); 5218 Assert(strcmp(g_aHdaRegMap[HDA_REG_SD7EFIFOS].pszName, "SD7EFIFOS") == 0); 5219 5220 /* 5221 * Register statistics. 5222 */ 5147 5223 # ifdef VBOX_WITH_STATISTICS 5148 /*5149 * Register statistics.5150 */5151 5224 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input."); 5152 5225 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output."); -
trunk/src/VBox/Devices/Audio/DevHda.h
r90140 r90158 111 111 112 112 /** Number of general registers. */ 113 #define HDA_NUM_GENERAL_REGS 34 113 #define HDA_NUM_GENERAL_REGS 36 114 /** Number of stream registers (10 registers per stream). */ 115 #define HDA_NUM_STREAM_REGS (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */) 116 /** Number of register after the stream registers. */ 117 #define HDA_NUM_POST_STREAM_REGS (2 + HDA_MAX_STREAMS * 2) 114 118 /** Number of total registers in the HDA's register map. */ 115 #define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))119 #define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + HDA_NUM_STREAM_REGS + HDA_NUM_POST_STREAM_REGS) 116 120 /** Total number of stream tags (channels). Index 0 is reserved / invalid. */ 117 121 #define HDA_MAX_TAGS 16 … … 186 190 #define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */ 187 191 188 #define HDA_REG_OUTSTRMPAY 9 /* 0x18 */ 192 #define HDA_REG_LLCH 9 /* 0x14 */ 193 #define HDA_RMX_LLCH 114 194 195 #define HDA_REG_OUTSTRMPAY 10 /* 0x18 */ 189 196 #define HDA_RMX_OUTSTRMPAY 112 190 197 191 #define HDA_REG_INSTRMPAY 1 0/* 0x1a */198 #define HDA_REG_INSTRMPAY 11 /* 0x1a */ 192 199 #define HDA_RMX_INSTRMPAY 113 193 200 194 #define HDA_REG_INTCTL 1 1/* 0x20 */201 #define HDA_REG_INTCTL 12 /* 0x20 */ 195 202 #define HDA_RMX_INTCTL 9 196 203 #define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */ … … 199 206 #define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */ 200 207 201 #define HDA_REG_INTSTS 1 2/* 0x24 */208 #define HDA_REG_INTSTS 13 /* 0x24 */ 202 209 #define HDA_RMX_INTSTS 10 203 210 #define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */ 204 211 #define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */ 205 212 206 #define HDA_REG_WALCLK 1 3/* 0x30 */207 /* *NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */213 #define HDA_REG_WALCLK 14 /* 0x30 */ 214 /* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */ 208 215 209 216 /** 210 * Note: The HDA specification defines a SSYNC register at offset 0x38. The211 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches212 * the datasheet.213 */ 214 #define HDA_REG_SSYNC 1 4/* 0x34 */217 * @note The HDA specification defines a SSYNC register at offset 0x38. The ICH6/ICH9 218 * datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches the datasheet. 219 * See also https://mailman.alsa-project.org/pipermail/alsa-devel/2011-March/037819.html 220 */ 221 #define HDA_REG_SSYNC 15 /* 0x34 */ 215 222 #define HDA_RMX_SSYNC 12 216 223 217 #define HDA_REG_CORBLBASE 15 /* 0x40 */ 224 #define HDA_REG_NEW_SSYNC 16 /* 0x38 */ 225 #define HDA_RMX_NEW_SSYNC HDA_RMX_SSYNC 226 227 #define HDA_REG_CORBLBASE 17 /* 0x40 */ 218 228 #define HDA_RMX_CORBLBASE 13 219 229 220 #define HDA_REG_CORBUBASE 1 6/* 0x44 */230 #define HDA_REG_CORBUBASE 18 /* 0x44 */ 221 231 #define HDA_RMX_CORBUBASE 14 222 232 223 #define HDA_REG_CORBWP 1 7/* 0x48 */233 #define HDA_REG_CORBWP 19 /* 0x48 */ 224 234 #define HDA_RMX_CORBWP 15 225 235 226 #define HDA_REG_CORBRP 18/* 0x4A */236 #define HDA_REG_CORBRP 20 /* 0x4A */ 227 237 #define HDA_RMX_CORBRP 16 228 238 #define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */ 229 239 230 #define HDA_REG_CORBCTL 19/* 0x4C */240 #define HDA_REG_CORBCTL 21 /* 0x4C */ 231 241 #define HDA_RMX_CORBCTL 17 232 242 #define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */ 233 243 #define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */ 234 244 235 #define HDA_REG_CORBSTS 2 0/* 0x4D */245 #define HDA_REG_CORBSTS 22 /* 0x4D */ 236 246 #define HDA_RMX_CORBSTS 18 237 247 238 #define HDA_REG_CORBSIZE 2 1/* 0x4E */248 #define HDA_REG_CORBSIZE 23 /* 0x4E */ 239 249 #define HDA_RMX_CORBSIZE 19 240 250 #define HDA_CORBSIZE_SZ_CAP 0xF0 … … 250 260 #define HDA_RIRB_ELEMENT_SIZE 8 251 261 252 #define HDA_REG_RIRBLBASE 2 2/* 0x50 */262 #define HDA_REG_RIRBLBASE 24 /* 0x50 */ 253 263 #define HDA_RMX_RIRBLBASE 20 254 264 255 #define HDA_REG_RIRBUBASE 2 3/* 0x54 */265 #define HDA_REG_RIRBUBASE 25 /* 0x54 */ 256 266 #define HDA_RMX_RIRBUBASE 21 257 267 258 #define HDA_REG_RIRBWP 2 4/* 0x58 */268 #define HDA_REG_RIRBWP 26 /* 0x58 */ 259 269 #define HDA_RMX_RIRBWP 22 260 270 #define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */ 261 271 262 #define HDA_REG_RINTCNT 2 5/* 0x5A */272 #define HDA_REG_RINTCNT 27 /* 0x5A */ 263 273 #define HDA_RMX_RINTCNT 23 264 274 … … 266 276 #define HDA_MAX_RINTCNT 256 267 277 268 #define HDA_REG_RIRBCTL 2 6/* 0x5C */278 #define HDA_REG_RIRBCTL 28 /* 0x5C */ 269 279 #define HDA_RMX_RIRBCTL 24 270 280 #define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */ … … 272 282 #define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */ 273 283 274 #define HDA_REG_RIRBSTS 2 7/* 0x5D */284 #define HDA_REG_RIRBSTS 29 /* 0x5D */ 275 285 #define HDA_RMX_RIRBSTS 25 276 286 #define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */ 277 287 #define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */ 278 288 279 #define HDA_REG_RIRBSIZE 28/* 0x5E */289 #define HDA_REG_RIRBSIZE 30 /* 0x5E */ 280 290 #define HDA_RMX_RIRBSIZE 26 281 291 282 #define HDA_REG_IC 29/* 0x60 */292 #define HDA_REG_IC 31 /* 0x60 */ 283 293 #define HDA_RMX_IC 27 284 294 285 #define HDA_REG_IR 3 0/* 0x64 */295 #define HDA_REG_IR 32 /* 0x64 */ 286 296 #define HDA_RMX_IR 28 287 297 288 #define HDA_REG_IRS 3 1/* 0x68 */298 #define HDA_REG_IRS 33 /* 0x68 */ 289 299 #define HDA_RMX_IRS 29 290 300 #define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */ 291 301 #define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */ 292 302 293 #define HDA_REG_DPLBASE 3 2/* 0x70 */303 #define HDA_REG_DPLBASE 34 /* 0x70 */ 294 304 #define HDA_RMX_DPLBASE 30 295 305 296 #define HDA_REG_DPUBASE 3 3/* 0x74 */306 #define HDA_REG_DPUBASE 35 /* 0x74 */ 297 307 #define HDA_RMX_DPUBASE 31 298 308 … … 309 319 310 320 #define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10) 321 #define HDA_SD_TO_REG(a_Name, uSD) (HDA_STREAM_REG_DEF(a_Name, 0) + (uSD) * 10) 311 322 312 323 /** @todo Condense marcos! */ … … 334 345 #define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */ 335 346 336 #define HDA_REG_SD0STS 35/* 0x83; other streams offset by 0x20 */347 #define HDA_REG_SD0STS (HDA_NUM_GENERAL_REGS + 1) /* 0x83; other streams offset by 0x20 */ 337 348 #define HDA_RMX_SD0STS 33 338 349 #define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10) … … 349 360 #define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */ 350 361 351 #define HDA_REG_SD0LPIB 36/* 0x84; other streams offset by 0x20 */362 #define HDA_REG_SD0LPIB (HDA_NUM_GENERAL_REGS + 2) /* 0x84; other streams offset by 0x20 */ 352 363 #define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */ 353 364 #define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */ … … 366 377 #define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70) 367 378 368 #define HDA_REG_SD0CBL 37/* 0x88; other streams offset by 0x20 */379 #define HDA_REG_SD0CBL (HDA_NUM_GENERAL_REGS + 3) /* 0x88; other streams offset by 0x20 */ 369 380 #define HDA_RMX_SD0CBL 35 370 381 #define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10) … … 376 387 #define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70) 377 388 378 #define HDA_REG_SD0LVI 38/* 0x8C; other streams offset by 0x20 */389 #define HDA_REG_SD0LVI (HDA_NUM_GENERAL_REGS + 4) /* 0x8C; other streams offset by 0x20 */ 379 390 #define HDA_RMX_SD0LVI 36 380 391 #define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10) … … 386 397 #define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70) 387 398 388 #define HDA_REG_SD0FIFOW 39/* 0x8E; other streams offset by 0x20 */399 #define HDA_REG_SD0FIFOW (HDA_NUM_GENERAL_REGS + 5) /* 0x8E; other streams offset by 0x20 */ 389 400 #define HDA_RMX_SD0FIFOW 37 390 401 #define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10) … … 403 414 #define HDA_SDFIFOW_32B 0x4 404 415 405 #define HDA_REG_SD0FIFOS 40/* 0x90; other streams offset by 0x20 */416 #define HDA_REG_SD0FIFOS (HDA_NUM_GENERAL_REGS + 6) /* 0x90; other streams offset by 0x20 */ 406 417 #define HDA_RMX_SD0FIFOS 38 407 418 #define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10) … … 427 438 #define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */ 428 439 429 #define HDA_REG_SD0FMT 41/* 0x92; other streams offset by 0x20 */440 #define HDA_REG_SD0FMT (HDA_NUM_GENERAL_REGS + 7) /* 0x92; other streams offset by 0x20 */ 430 441 #define HDA_RMX_SD0FMT 39 431 442 #define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10) … … 437 448 #define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70) 438 449 439 #define HDA_REG_SD0BDPL 42/* 0x98; other streams offset by 0x20 */450 #define HDA_REG_SD0BDPL (HDA_NUM_GENERAL_REGS + 8) /* 0x98; other streams offset by 0x20 */ 440 451 #define HDA_RMX_SD0BDPL 40 441 452 #define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10) … … 447 458 #define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70) 448 459 449 #define HDA_REG_SD0BDPU 43/* 0x9C; other streams offset by 0x20 */460 #define HDA_REG_SD0BDPU (HDA_NUM_GENERAL_REGS + 9) /* 0x9C; other streams offset by 0x20 */ 450 461 #define HDA_RMX_SD0BDPU 41 451 462 #define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10) … … 513 524 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \ 514 525 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK)) 526 527 528 /* Post stream registers: */ 529 #define HDA_REG_MLCH (HDA_NUM_GENERAL_REGS + HDA_NUM_STREAM_REGS) /* 0xc00 */ 530 #define HDA_RMX_MLCH 115 531 #define HDA_REG_MLCD (HDA_REG_MLCH + 1) /* 0xc04 */ 532 #define HDA_RMX_MLCD 116 533 534 /* Registers added/specific-to skylake/broxton: */ 535 #define HDA_SD_NUM_FROM_SKYLAKE_REG(a_Name, a_iMap) (((a_iMap) - HDA_STREAM_REG_DEF(a_Name, 0)) / 2) 536 537 #define HDA_REG_SD0DPIB (HDA_REG_MLCD + 1) /* 0x1084 */ 538 #define HDA_REG_SD1DPIB (HDA_REG_SD0DPIB + 1*2) 539 #define HDA_REG_SD2DPIB (HDA_REG_SD0DPIB + 2*2) 540 #define HDA_REG_SD3DPIB (HDA_REG_SD0DPIB + 3*2) 541 #define HDA_REG_SD4DPIB (HDA_REG_SD0DPIB + 4*2) 542 #define HDA_REG_SD5DPIB (HDA_REG_SD0DPIB + 5*2) 543 #define HDA_REG_SD6DPIB (HDA_REG_SD0DPIB + 6*2) 544 #define HDA_REG_SD7DPIB (HDA_REG_SD0DPIB + 7*2) 545 546 #define HDA_RMX_SD0DPIB HDA_RMX_SD0LPIB 547 #define HDA_RMX_SD1DPIB HDA_RMX_SD1LPIB 548 #define HDA_RMX_SD2DPIB HDA_RMX_SD2LPIB 549 #define HDA_RMX_SD3DPIB HDA_RMX_SD3LPIB 550 #define HDA_RMX_SD4DPIB HDA_RMX_SD4LPIB 551 #define HDA_RMX_SD5DPIB HDA_RMX_SD5LPIB 552 #define HDA_RMX_SD6DPIB HDA_RMX_SD6LPIB 553 #define HDA_RMX_SD7DPIB HDA_RMX_SD7LPIB 554 555 #define HDA_REG_SD0EFIFOS (HDA_REG_SD0DPIB + 1) /* 0x1094 */ 556 #define HDA_REG_SD1EFIFOS (HDA_REG_SD0EFIFOS + 1*2) 557 #define HDA_REG_SD2EFIFOS (HDA_REG_SD0EFIFOS + 2*2) 558 #define HDA_REG_SD3EFIFOS (HDA_REG_SD0EFIFOS + 3*2) 559 #define HDA_REG_SD4EFIFOS (HDA_REG_SD0EFIFOS + 4*2) 560 #define HDA_REG_SD5EFIFOS (HDA_REG_SD0EFIFOS + 5*2) 561 #define HDA_REG_SD6EFIFOS (HDA_REG_SD0EFIFOS + 6*2) 562 #define HDA_REG_SD7EFIFOS (HDA_REG_SD0EFIFOS + 7*2) 563 564 #define HDA_RMX_SD0EFIFOS 117 565 #define HDA_RMX_SD1EFIFOS (HDA_RMX_SD0EFIFOS + 1) 566 #define HDA_RMX_SD2EFIFOS (HDA_RMX_SD0EFIFOS + 2) 567 #define HDA_RMX_SD3EFIFOS (HDA_RMX_SD0EFIFOS + 3) 568 #define HDA_RMX_SD4EFIFOS (HDA_RMX_SD0EFIFOS + 4) 569 #define HDA_RMX_SD5EFIFOS (HDA_RMX_SD0EFIFOS + 5) 570 #define HDA_RMX_SD6EFIFOS (HDA_RMX_SD0EFIFOS + 6) 571 #define HDA_RMX_SD7EFIFOS (HDA_RMX_SD0EFIFOS + 7) 515 572 516 573 /** @} */ /* grp_hda_regs */
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