Changeset 90380 in vbox

Timestamp:

Jul 28, 2021 9:38:23 PM (3 years ago)

Author:

vboxsync

Message:

VMM: Moved idHostCpu and iHostCpuSet from VMCPU to GVMCPU, removing the VMMR0PERVCPU copies too. bugref:6695

Location:

trunk

Files:

• include/VBox/vmm/gvm.h (modified) (2 diffs)
• include/VBox/vmm/gvm.mac (modified) (2 diffs)
• include/VBox/vmm/vm.h (modified) (1 diff)
• include/VBox/vmm/vm.mac (modified) (1 diff)
• src/VBox/VMM/VMMAll/TMAllCpu.cpp (modified) (1 diff)
• src/VBox/VMM/VMMR0/VMMR0.cpp (modified) (13 diffs)
• src/VBox/VMM/include/VMMInternal.h (modified) (1 diff)
• src/VBox/VMM/testcase/tstVMStruct.h (modified) (1 diff)

trunk/include/VBox/vmm/gvm.h

@@ -57 +57 @@
 
     /** VCPU id (0 - (pVM->cCpus - 1). */
-    VMCPUID         idCpu;
+    VMCPUID             idCpu;
     /** Padding. */
-    uint32_t        uPadding;
+    uint32_t            uPadding0;
 
     /** Handle to the EMT thread. */
-    RTNATIVETHREAD  hEMT;
+    RTNATIVETHREAD      hEMT;
 
     /** Pointer to the global (ring-0) VM structure this CPU belongs to. */
-    R0PTRTYPE(PGVM) pGVM;
+    R0PTRTYPE(PGVM)     pGVM;
     /** Pointer to the GVM structure, for CTX_SUFF use in VMMAll code.  */
-    PGVM            pVMR0;
+    PGVM                pVMR0;
     /** The ring-3 address of this structure (only VMCPU part). */
-    PVMCPUR3        pVCpuR3;
+    PVMCPUR3            pVCpuR3;
+
+    /** Padding so the noisy stuff on a 64 byte boundrary.
+     * @note Keeping this working for 32-bit header syntax checking.  */
+    uint8_t             abPadding1[HC_ARCH_BITS == 32 ? 40 : 24];
+
+    /** Which host CPU ID is this EMT running on.
+     * Only valid when in RC or HMR0 with scheduling disabled. */
+    RTCPUID volatile    idHostCpu;
+    /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
+     * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
+    uint32_t volatile   iHostCpuSet;
 
     /** Padding so gvmm starts on a 64 byte boundrary.
      * @note Keeping this working for 32-bit header syntax checking.  */
-    uint8_t         abPadding[HC_ARCH_BITS == 32 ? 40 : 24];
+    uint8_t             abPadding2[56];
 
     /** The GVMM per vcpu data. */
@@ -109 +120 @@
         struct VMMR0PERVCPU s;
 #endif
-        uint8_t             padding[128];
+        uint8_t             padding[64];
     } vmmr0;
 
     /** Padding the structure size to page boundrary. */
 #ifdef VBOX_WITH_NEM_R0
-    uint8_t                 abPadding2[4096 - 64 - 64 - 1024 - 64 - 128];
+    uint8_t                 abPadding3[4096 - 64*2 - 64 - 1024 - 64 - 64];
 #else
-    uint8_t                 abPadding2[4096 - 64 - 64 - 1024 - 128];
+    uint8_t                 abPadding3[4096 - 64*2 - 64 - 1024 - 64];
 #endif
 } GVMCPU;

trunk/include/VBox/vmm/gvm.mac

@@ -40 +40 @@
 
         alignb 64
+        .idHostCpu          resd 1
+        .iHostCpuSet        resd 1
+
+        alignb 64
         .gvmm               resb 64
         alignb 64
@@ -47 +51 @@
 %endif
         alignb 64
-        .vmmr0              resb 128
+        .vmmr0              resb 64
         alignb 4096
 endstruc

trunk/include/VBox/vmm/vm.h

@@ -120 +120 @@
     VMCPUSTATE volatile     enmState;
 
-    /** Which host CPU ID is this EMT running on.
-     * Only valid when in RC or HMR0 with scheduling disabled. */
-    RTCPUID volatile        idHostCpu;
-    /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
-     * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
-    uint32_t volatile       iHostCpuSet;
     /** Padding up to 64 bytes. */
-    uint8_t                 abAlignment0[64 - 20];
+    uint8_t                 abAlignment0[64 - 12];
     /** @} */
 

trunk/include/VBox/vmm/vm.mac

@@ -46 +46 @@
     alignb 8
     .enmState               resd 1
-    .idHostCpu              resd 1
-    .iHostCpuSet            resd 1
 
     alignb 64

trunk/src/VBox/VMM/VMMAll/TMAllCpu.cpp

@@ -368 +368 @@
  *                          sync deadline.
  */
-DECLINLINE(uint64_t) tmCpuCalcTicksToDeadline(PVMCPU pVCpu, uint64_t cNsToDeadline)
+DECLINLINE(uint64_t) tmCpuCalcTicksToDeadline(PVMCPUCC pVCpu, uint64_t cNsToDeadline)
 {
     AssertCompile(TMCLOCK_FREQ_VIRTUAL <= _4G);

trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

@@ -368 +368 @@
     {
         PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
-        pGVCpu->vmmr0.s.idHostCpu       = NIL_RTCPUID;
-        pGVCpu->vmmr0.s.iHostCpuSet     = UINT32_MAX;
+        Assert(pGVCpu->idHostCpu == NIL_RTCPUID);
+        Assert(pGVCpu->iHostCpuSet == UINT32_MAX);
         pGVCpu->vmmr0.s.fInHmContext    = false;
         pGVCpu->vmmr0.s.pPreemptState   = NULL;
@@ -1006 +1006 @@
             RTCPUID idHostCpu;
             uint32_t iHostCpuSet = RTMpCurSetIndexAndId(&idHostCpu);
-            pVCpu->vmmr0.s.iHostCpuSet = iHostCpuSet;
-            ASMAtomicWriteU32(&pVCpu->vmmr0.s.idHostCpu, idHostCpu);
             pVCpu->iHostCpuSet = iHostCpuSet;
             ASMAtomicWriteU32(&pVCpu->idHostCpu, idHostCpu);
@@ -1036 +1034 @@
              * have the same host CPU associated with it.
              */
-            pVCpu->vmmr0.s.iHostCpuSet = UINT32_MAX;
-            ASMAtomicWriteU32(&pVCpu->vmmr0.s.idHostCpu, NIL_RTCPUID);
             pVCpu->iHostCpuSet = UINT32_MAX;
             ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
@@ -1109 +1105 @@
  * @thread  EMT(pVCpu)
  *
- * @remarks This also clears VMCPU::idHostCpu, so the mapping is invalid after
+ * @remarks This also clears GVMCPU::idHostCpu, so the mapping is invalid after
  *          this call.  This means you have to be careful with what you do!
  */
@@ -1121 +1117 @@
      *      hmR0VmxLeaveSession/hmR0SvmLeaveSession disables context hooks during
      *      longjmp & normal return to ring-3, which opens a window where we may be
-     *      rescheduled without changing VMCPUID::idHostCpu and cause confusion if
+     *      rescheduled without changing GVMCPUID::idHostCpu and cause confusion if
      *      the CPU starts executing a different EMT.  Both functions first disables
      *      preemption and then calls HMR0LeaveCpu which invalids idHostCpu, leaving
@@ -1128 +1124 @@
     /** @todo Make HM not need this API!  Then we could leave the hooks enabled
      *        all the time. */
-    /** @todo move this into the context hook disabling if(). */
-    ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
 
     /*
@@ -1137 +1131 @@
     {
         Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
-        ASMAtomicWriteU32(&pVCpu->vmmr0.s.idHostCpu, NIL_RTCPUID);
+        ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
         int rc = RTThreadCtxHookDisable(pVCpu->vmmr0.s.hCtxHook);
         AssertRC(rc);
@@ -1458 +1452 @@
                               && SUPIsTscDeltaAvailableForCpuSetIndex(iHostCpuSet)))
                 {
-                    pGVCpu->vmmr0.s.iHostCpuSet = iHostCpuSet;
-                    ASMAtomicWriteU32(&pGVCpu->vmmr0.s.idHostCpu, idHostCpu);
-
                     pGVCpu->iHostCpuSet = iHostCpuSet;
                     ASMAtomicWriteU32(&pGVCpu->idHostCpu, idHostCpu);
@@ -1552 +1543 @@
                          * hook / restore preemption.
                          */
-                        pGVCpu->vmmr0.s.iHostCpuSet = UINT32_MAX;
-                        ASMAtomicWriteU32(&pGVCpu->vmmr0.s.idHostCpu, NIL_RTCPUID);
-
                         pGVCpu->iHostCpuSet = UINT32_MAX;
                         ASMAtomicWriteU32(&pGVCpu->idHostCpu, NIL_RTCPUID);
@@ -1566 +1554 @@
                          */
                         if (pGVCpu->vmmr0.s.hCtxHook != NIL_RTTHREADCTXHOOK)
-                        {
-                            ASMAtomicWriteU32(&pGVCpu->idHostCpu, NIL_RTCPUID);
                             RTThreadCtxHookDisable(pGVCpu->vmmr0.s.hCtxHook);
-                        }
                     }
                     /*
@@ -1576 +1561 @@
                     else
                     {
-                        rc = VINF_EM_RAW_INTERRUPT;
                         pGVCpu->iHostCpuSet = UINT32_MAX;
                         ASMAtomicWriteU32(&pGVCpu->idHostCpu, NIL_RTCPUID);
+                        rc = VINF_EM_RAW_INTERRUPT;
                     }
 
@@ -1618 +1603 @@
                 {
                     pGVCpu->vmmr0.s.pPreemptState = NULL;
-                    pGVCpu->vmmr0.s.iHostCpuSet = UINT32_MAX;
-                    ASMAtomicWriteU32(&pGVCpu->vmmr0.s.idHostCpu, NIL_RTCPUID);
                     pGVCpu->iHostCpuSet = UINT32_MAX;
                     ASMAtomicWriteU32(&pGVCpu->idHostCpu, NIL_RTCPUID);
@@ -2635 +2618 @@
          * Are we in HM context and w/o a context hook?  If so work the context hook.
          */
-        if (pVCpu->vmmr0.s.idHostCpu != NIL_RTCPUID)
-        {
-            Assert(pVCpu->vmmr0.s.iHostCpuSet != UINT32_MAX);
+        if (pVCpu->idHostCpu != NIL_RTCPUID)
+        {
+            Assert(pVCpu->iHostCpuSet != UINT32_MAX);
             Assert(pVCpu->vmmr0.s.fInHmContext);
 

trunk/src/VBox/VMM/include/VMMInternal.h

@@ -460 +460 @@
 typedef struct VMMR0PERVCPU
 {
-    /** Which host CPU ID is this EMT running on.
-     * Only valid when in RC or HMR0 with scheduling disabled. */
-    RTCPUID volatile                    idHostCpu;
-    /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
-     * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
-    uint32_t volatile                   iHostCpuSet;
     /** Set if we've entered HM context. */
     bool volatile                       fInHmContext;

trunk/src/VBox/VMM/testcase/tstVMStruct.h

@@ -1458 +1458 @@
     GEN_CHECK_OFF(VMCPU, hNativeThread);
     GEN_CHECK_OFF(VMCPU, hNativeThreadR0);
-    GEN_CHECK_OFF(VMCPU, idHostCpu);
     GEN_CHECK_OFF(VMCPU, fTraceGroups);
     GEN_CHECK_OFF(VMCPU, uAdHoc);